ADC mode of operation: CPOL and CPHA

[raff5184]

Hi
I'm trying to understand the mode of operation of the ADS 7883 ADC converter.
http://www.ti.com/lit/ds/symlink/ads7883.pdf

But from the diagram on page 9, I can't actually tell because the SDO data are not exactly in correspondence of the falling or rising edge of the SCLK.
I think the CPOL is 1 (look at the beginning of the SCLK signal, it's high) but what about the CPHA?

Thank you

[imisaac]

Looking at the timing diagram of the datasheet, the data bit is sampled at the falling edge. So, I guess the CPHAS=1.

That is, I think that the SPI mode 3 (CPOL=1, CPHAS=1) may work for this ADC.

[raff5184]

that's what I eventually realized.
Another question, can I use a CLK at 4 MHz or 8MHz, or do I necessarily need to use a 32MHz clock (at 3.3V)?

[Bassman59]

that's what I eventually realized.
Another question, can I use a CLK at 4 MHz or 8MHz, or do I necessarily need to use a 32MHz clock (at 3.3V)?

The SPI clock also determines the sample rate, so if your application can work with a reduced sample rate, then it should be fine.