Hello,
From what I understand, using a N-channel enhancement mode MOSFET with a couple of pull up resistors to do level translation can be pretty slow, due to the RC load that is created between the pull up resistors and the input/output capacitance of the transistor, resulting in a delay when switching between high and low logic levels.
For instance, as seen in Fig 1, an AO3400 has a pretty big Ciss of 630pF and a Coss of 75pF which would make it a pretty poor choice compared something like a BSS138 (Ciss 27pF and Coss 13pF).
Now, this level shifting circuit looks pretty much like a discrete NMOS circuit with passive loads. So in theory it should be possible to replace the passive loads with N-channel depletion mode MOSFETs similarly to Fig 2.
In such a case, would an active load actually improve the speed of operation of the level shifter, regardless of the transistor used for the translation? And would such active load configuration also benefit discrete NMOS implementations compared to ones with passive loads?