JFET Switch Biasing

[eev_carl]

Hi,

In this schematic, it looks like the Gate will receive a positive voltage as the switch is flipped up to V+.  Won't this damage the N-Channel JFET?



I'm referencing Figure 6 in the original article here: http://www.nutsvolts.com/magazine/article/fet_principles_and_circuits_part_1 .

Thanks,
Carl

[Zero999]

Yes, if the gate current is not limited, it will damage the J-FET because the gate diode junction will be forward biased and a huge current will flow. If the gate is connected to +V via a high value resistor, say 10M, it will conduct more current, than it would if the gate were connected to 0V: it's possible to run J-FET in enhancement mode to some extent.

The gate will need to be connected to a negative voltage to turn the J-FET fully off.

I couldn't get the link to work, perhaps they've confused J-FETs with MOSFETs?

[eev_carl]

Hi, The link is fixed (darn trailing period!).

[Cerebus]

I couldn't get the link to work, perhaps they've confused J-FETs with MOSFETs?

Or they have drawn an N-channel JFET when they meant to draw a P-channel JFET, even then it's still a bit off as the load is poorly defined.

The switch polarity is completely wrong for an N-channel JFET, in the position labelled 'off' the gate junction will be forward biased and thus the channel fully on. In the position labelled 'on' the gate junction will have no reverse bias and so the channel will still be fully on.

Change it to a P-channel JFET and there's no junction bias in either forward or reverse directions in the 'on' position so the channel will be on and there's no possibility of pushing too much current through the gate junction. In the 'off' position a P-channel gate junction would be reverse biased and thus the channel would be off - with the provision that 'V+' is high enough voltage, but not too high.

[Zero999]

Hi, The link is fixed (darn trailing period!).

Still not fixed. Here's the corrected link:
http://www.nutsvolts.com/magazine/article/fet_principles_and_circuits_part_1

I couldn't get the link to work, perhaps they've confused J-FETs with MOSFETs?

Or they have drawn an N-channel JFET when they meant to draw a P-channel JFET, even then it's still a bit off as the load is poorly defined.

The switch polarity is completely wrong for an N-channel JFET, in the position labelled 'off' the gate junction will be forward biased and thus the channel fully on. In the position labelled 'on' the gate junction will have no reverse bias and so the channel will still be fully on.

Change it to a P-channel JFET and there's no junction bias in either forward or reverse directions in the 'on' position so the channel will be on and there's no possibility of pushing too much current through the gate junction. In the 'off' position a P-channel gate junction would be reverse biased and thus the channel would be off - with the provision that 'V+' is high enough voltage, but not too high.

Yes, looking at it again, it's total nonsense, as you say, the switch positions are incorrectly marked. For it to work properly for a P-FET, the drain would also have to be biased with a negative voltage. It seems there's been a bit mix-up here.

[Alex Nikitin]

Yes, looking at it again, it's total nonsense, as you say, the switch positions are incorrectly marked. For it to work properly for a P-FET, the drain would also have to be biased with a negative voltage. It seems there's been a bit mix-up here.

The "V+" should be negative, than the circuit should work. There are many errors in that article  . 

Cheers

Alex

[eev_carl]

Sorry about the link everyone.  I missed the period in the link tag when I went back over it and just fixed the label.

It's too bad about the article because it seemed to cover so much of what I was interested in.