The "boundary" is between the P-doped and N-doped regions.
The depletion layer forms on both sides of that boundary: at zero bias, the depletion layer forms normally to a finite thickness. Applying a reverse bias will increase the thickness of the depletion region.
One example of this is a diode (varicap or varactor or tuning diode) that is optimized for use as a variable capacitor: the capacitance at zero bias is relatively large (thin depletion region) and increasing the reverse bias causes this capacitance to decrease.
the depletion layer forms BETWEEN the boundaries.
The
BETWEEN the boundaries isn't correct!! As TimFox mentioned, under no bias the depletion region or layer extends beyond or OUTSIDE the boundary or semiconductor interface where the mobile charges are depleted. Under reverse bias conditions this depletion region extends further and can be "viewed" as somewhat like parallel plates of a capacitor with separation (depletion region) under voltage control. Under forward bias conditions the depletion region collapses and you have available mobile carriers and current flow.
A simple thought experiment will show that if you have a pair of doped semiconductors, one is P type the other is N type. When you bring these separate doped semiconductor "faces" into contact, the boundary is obviously the physical interface between the two semiconductors, however the depletion region extends into both semiconductors from the boundary interface in both directions. You can calculate the depletion region width based upon Poisson's and Gauss's Law, see below.
From Wiki:
https://en.wikipedia.org/wiki/Depletion_regionAnyway, hopefully, this will make things a little clearer for the OP which is everyone's intent
Best,
Edit: Semiconductor physics can be daunting at first, but if you can make analogies and think in terms of more common things then it becomes much clearer. For instance, even the very complex Silicon Germanium bipolar transistors with the base emitter band-gap engineering can be understood as having an electric field of such magnitude that the carriers are quickly swept across the junction by the high fields, thus improved speed. These junctions can even be tailored to produce super-beta bipolar devices, or even possible devices where no base bias is required for significant collector emitter current flow (although don't recall anyone ever trying this).
Another example is when IBM used Germamium in CMOS to tweak the lattice structure by means of induced strain due to the lattice mismatch between Silicon and Germanium. This was what we used to call Ballistic CMOS where the free carriers flew down the channel like a bullet in a barrel with much fewer collisions, or in semiconductor terms the carrier mean free path became larger.