Immediate success nearly guaranteed with .03" (.75mm) even for a beginner.
Yes, it does take practice. but I was able to get regularly get a trace between CMOS DIP chip pads and 3 traces down the middle of a 4011 CMOS.
I get at least 8x 8 mil traces down the middle of a standard DIP without even optimizing. Just routing free hand, uneven, and then doing a DRC to check for minimum 8 mil clearance. I can get probably 9 if I take the time to space them evenly. With oval through hole pads, I can run 2 traces between pads. But I don't use any DIP IC's for the last 5 years. This isn't "pushing it." If it takes special attention, I avoid doing it. This is business as usual.
But I always tried to keep those super thin lines as short as possible.
I often make my traces much bigger than 8 mil. If it doesn't really matter for the layout, I tend to make the traces bigger, even on factory ordered boards. Actually it makes it easier. If you use 8 mil traces but the IC has wider spacing, then you "have to" bunch your traces together and then fan them out again.* But when I use an 8 mil trace that isn't carrying a high current, I make it 8 mil all the way. Making the trace thinner in only one spot makes it look funny, and I have the impression it increases the chance that the short thin section overetches.
*The only thing I try to avoid is running a skinny 8 mil trace all by itself with nothing around it. This is one of the things that can be iffy. Ground pours take care of that problem. This is also why you "have to" bunch skinny traces together and fan them back out. Else you get slivers of ground pour between them, anyway. And if you leave them too widely spaced with blank space between them, by
say increasing your trace clearances, this can etch funny. Bigger traces, you can use any clearance you want. But IME, when your traces get smaller than 12, you want the clearance to be roughly the same size as the trace thickness at most, but you can make them smaller if you want, down to w/e resolution you can get with your methods and etchant.
It's a strange thing where you start out making giant boards with fat traces with giant clearances. But as you shrink your clearances, the etch comes out better. And you can get way more stuff in a smaller space. And getting the board done in a smaller space also increases your yield, because it's less area for an error. Experimenting with reducing clearances, you may find this can be more important to the yield than the trace width, and the fat traces are no longer necessary. It may be initially uncomfortable to solder a board with tight clearances, but you can use larger clearances just around the pads without compromising the results by much. Heck, it looks "bad" at first, like it will be harder to detect bridges. But thinner clearances etch faster and cleaner and you don't have to look as hard. Higher consistency and clean edges means less (or even no) inspection. I really don't but glance at a board and call it good. If you etch a single-sided board on double-sided copper, you know the blank side not only takes forever to etch, but one area of the blank side becomes clear way before the last bit etches away. Large enough clearance, and that also slows down and "unevens" the etching and can lead to chewy traces.
I have heard some people using toner transfer do 12/18... 12 is fine to use oversize clearance. I think these peeps need extra clearance because they are either fattening their traces during the transfer and/or they are using fuzzy paper that leaves fibers. If your process and etchant are up to snuff, once you get comfortable with looking at and assembling boards with tight clearances, the process goes to the next level and is extremely reliable. I haven't have to repair or redo a board in probably 5 years.