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Electronics => Beginners => Topic started by: soFPG on July 17, 2020, 04:41:17 pm

Title: Buck Converter capacitor calculation
Post by: soFPG on July 17, 2020, 04:41:17 pm

My plan was to use a JW5033S buck converter (datasheet: https://datasheet.lcsc.com/szlcsc/1906281506_JoulWatt-Tech-JW5033S_C324577.pdf).

Unfortunately, I am not an electrical engineer and I don't understand how to calculate values for capacitors. According to the datasheet, they affect "ripple voltage".
So, is ripple voltage a good or a bad thing? Should it be high or low?

I attached my current schematic. The JW5033S is supposed to run at 2.8V and power a MachXO2 Lattice FPGA, an image sensor (~20mA) as well as a small microcontroller.
At the moment, I just adopted the values from the datasheet and only changed the voltage divider.

Title: Re: Buck Converter capacitor calculation
Post by: T3sl4co1l on July 17, 2020, 05:01:04 pm

Uh, inductor is on the wrong side...!

Ripple is undesirable, but because the control is internally compensated, you have no adjustments to allow other component values.  Use the recommended values.

If you need lower ripple (as you might for the FPGA's PLL, say?), add additional LC filtering.

Tim

Title: Re: Buck Converter capacitor calculation
Post by: soFPG on July 17, 2020, 05:07:04 pm

Thanks for the inductor hint :)

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If you need lower ripple (as you might for the FPGA's PLL, say?), add additional LC filtering.

I have multiple bypass capacitors (100nF - 22uF) for the FPGA - shouldn't they act as a form of lowpass filter e.g. eliminating high frequency ripple?

Title: Re: Buck Converter capacitor calculation
Post by: T3sl4co1l on July 17, 2020, 05:16:49 pm

Maybe.  Relevant discussion: https://www.eevblog.com/forum/projects/location-and-value-of-decoupling-capacitors-(not-bga)/ (https://www.eevblog.com/forum/projects/location-and-value-of-decoupling-capacitors-(not-bga)/)

Bypasses should generally behave as a lowpass transmission line, but there can be modes at high frequencies as well.

Within the lower passband, there can be plenty of ripple.  Ripple can introduce jitter for example, because gate input thresholds are proportional to supply voltage.  Probably doesn't matter.  But then, say if your image sensor is internally clocked so you need to synchronize your clock to it -- it might be a concern after all.

Tim

Title: Re: Buck Converter capacitor calculation
Post by: soFPG on July 17, 2020, 06:46:04 pm

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But then, say if your image sensor is internally clocked so you need to synchronize your clock to it

The image sensor receives its clock from an external pin. My plan was to generate that clock with the FPGA.

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Relevant discussion:

Thank you