Building a mux/demux circuit. Help please!

[Armin_Balija]

Greetings Forum,

I come today asking for help on my project for school for digital class. We have to build a multiplexer/demultiplexer circuit that uses flip-flops (of our choice) to store 4 bits of data, on 4 different registers, then send them off through a mux/demux and have them arrive on other side in the correct order and registers.

I've built the circuit up using four 74165N IC's ((D Flip-Flop )PISO)) to hold my data and send it off.

I'm using a 74153N Multiplexer and a 74155N Demultiplexer.

I'm using four 7476N JK flip-flops as a binary counter for my data selector switch.

So far all of this will work with a manual selector switch for the mux/demux but I run into trouble once I try connecting my binary counter to the mux/demux as a selector switch, which is what is required for the project.

The problem I encounter when I connect my binary counter to my circuit is that I get lots of data crossover and data trying to get through at the same time or incomplete data. I've set up 4 more counters that count at 1/4 the frequency as my selector switch but I'm not too sure that my gating is correct on my other counters that would prevent my information to get through.

I'm using MultiSim 11.0 (which we use at our school) to construct the circuit. Here is the circuit in MS 11.0 but I doubt anyone actually uses it anymore .

http://www.megaupload.com/?d=49SUKWUP

Please let me know what I'm doing wrong because I'm the only one in my group at school doing anything and it's a pain when I don't get help from my group mates. I'm trying my best but it seems there's something I'm just not getting. I'm assuming all my gates are messed up or I'm not setting them up correctly.

[Psi]

i've not read the circuit, but are you sure you've got the data being clocked on a consistent edge (rise or fall)

[sub]

i've not read the circuit, but are you sure you've got the data being clocked on a consistent edge (rise or fall)

If your multiplexers/demultiplexers are clocked in phase with the data, you might run into timing issues.  As a quick test, perhaps try inverting the clock of the counter that drives the muxes.

[Armin_Balija]

i've not read the circuit, but are you sure you've got the data being clocked on a consistent edge (rise or fall)

If your multiplexers/demultiplexers are clocked in phase with the data, you might run into timing issues.  As a quick test, perhaps try inverting the clock of the counter that drives the muxes.

That seemed to help a bit as more data was being pulsed through. What I'm trying to do is run the 4 extra counters through gates that will shut off the previous gate when the counter reaches the end of it's cycle. Hmm