Building a pulse generator: puzzled by PCB trace impedance matching

[shapirus]

I'm considering re-spinning the board on 4 layers, just for the hell of it and to learn KiCAD. But first I want to understand how solid Vcc/Gnd planes resonate, and how to damp that.

Ha. I am going to do a VCC copper pour on the upper layer. It will add another 30-40 pF of distributed capacitance (size of the board is only 33 mm x 53 mm, I designed it for a specific housing), so in terms of energy it's not going to help much, but it might help that fast edge a little bit -- who knows what impedance it'll have at the target frequency. It is considered to be useless to design for interplanar capacitance, unless the dielectric between the planes is really thin (say 0.2 mm or less), but I'm gonna try it anyway. It can't hurt, unless... I'll keep an eye on the resonance/ringing that you mentioned, and experimenting with that is another purpose of trying the VCC copper pour. My intuition, however, tells me that the effects, if there will be any at all, will not be measurable/observable with my DHO804 (enhanced to DHO924 sans AWG&LA), and I'd need a much more advanced scope for that.

[shapirus]

and watch out for the capacitor's value when it has 5V across it. You can "lose" >80% of the capacitance that way, so check the specs

Yes lol I haven't yet finished my tester of the MLCC capacitanse loss under DC bias, it still sits almost fully functional on a solderless breadboard. I will, eventually, but now I have more interest in this pulser.

I have a lot of 100 uF 1206 ceramics from aliexpress -- even their working voltage is not specified, let alone capacitance curves lol. I've measured their breakdown voltage at ~70 V, so they'll be fine in this regard for 5 V, but since they are likely rated for 6.3 V (at best), I'll consider their capacity at 5 V to be say 20% of the zero-bias one, whack more of them on the board, and call it a day.

These are only for bulk energy storage / filtering, of course. For IC decoupling, I've got some better 0805 caps, some C0G/NP0, where they were available for given values, otherwise X7R, with known working voltages. I have yet to decide which values to use, though.

[tggzzz]

I'm considering re-spinning the board on 4 layers, just for the hell of it and to learn KiCAD. But first I want to understand how solid Vcc/Gnd planes resonate, and how to damp that.

Ha. I am going to do a VCC copper pour on the upper layer. It will add another 30-40 pF of distributed capacitance (size of the board is only 33 mm x 53 mm, I designed it for a specific housing), so in terms of energy it's not going to help much, but it might help that fast edge a little bit -- who knows what impedance it'll have at the target frequency. It is considered to be useless to design for interplanar capacitance, unless the dielectric between the planes is really thin (say 0.2 mm or less), but I'm gonna try it anyway. It can't hurt, unless... I'll keep an eye on the resonance/ringing that you mentioned, and experimenting with that is another purpose of trying the VCC copper pour. My intuition, however, tells me that the effects, if there will be any at all, will not be measurable/observable with my DHO804 (enhanced to DHO924 sans AWG&LA), and I'd need a much more advanced scope for that.

...0.2mm... How thick is prepreg on a 4-layer board?

[shapirus]

...0.2mm... How thick is prepreg on a 4-layer board?

No idea. I'm staying away from 4-layer for the time being, there's a lot to swallow as it is besides them for me.

But in any case, interplanar capacitance will make more sense on a 4-layer board than on a 2-layer one, that's for sure. Exactly how much more is a different question.

[David Hess]

It's probably diminishing returns at this point, unless a better package was used other than SOIC to help reduce inductance. It might improve the shape too, since there could be interactions due to discrepancies in length of signals due to the SOIC package, which I didn't take into account.

No, the parasitic elements of the SOIC package are not the problem, although they will affect the rise time, but I have an idea of what is going on.

When the CMOS switches, it connects Vcc or Gnd to the output, so any irregularities on Gnd or Vcc get transferred to the output.  What we are seeing is Vcc or Gnd being disturbed, which is also why pre-shoot is getting through.  The solution is to reduce the impedance between Vcc and Gnd.  It might be that shoot-through currents in the output driver are ringing Vcc and Gnd.

Better pulse generators use a different type of circuit with current switching and parallel termination instead of voltage switching and series termination, and since the current is constant, the power supply is not disturbed when switching occurs.

I would add a ceramic and tantalum across the top of the package directly between the Vcc and Gnd pins, with some low inductance wire or copper tape.  This probably will not solve it completely, but it should improve the situation.  A better power and ground layout would be necessary to fix it, and even that won't be as good as the current based solution that I mentioned.

[shapirus]

And finally added a 1nF capacitor using that diagonal wire over the chip, to try to reduce inductance in at least some of the decoupling.

Yes, that creates about the shortest inductance loop you can get. The way to do it without that bodge wire is to mount the capacitor(s) on the other side of the board, right under the chip, diagonally, and use a via to route the VCC pin to that bottom side. Makes sense to use via in pad, both sides, same for the ground pin.

[David Hess]

And finally added a 1nF capacitor using that diagonal wire over the chip, to try to reduce inductance in at least some of the decoupling.

Yes, that creates about the shortest inductance loop you can get. The way to do it without that bodge wire is to mount the capacitor(s) on the other side of the board, right under the chip, diagonally, and use a via to route the VCC pin to that bottom side. Makes sense to use via in pad, both sides, same for the ground pin.

I suggested the same thing but along the top because it is not clear what access close to the supply pins is available on the bottom of the board.

I have seen dead bug and Manhattan style construction used for this circuit which had much better results, which suggests a problem with the layout.

[shapirus]

Better pulse generators use a different type of circuit with current switching and parallel termination instead of voltage switching and series termination, and since the current is constant, the power supply is not disturbed when switching occurs.

That's quite interesting, but:

1) it assumes that the load impedance is constant, right? Not much of a problem, though, as they are typically designed to drive a 50 ohm load anyway.

2) it's terrible in terms of energy efficiency. But only in a relative way. In absolute numbers it's probably just fine, since, again, we only need to drive 50 ohm at a low voltage, so who cares if we consume two times the power, when it still stays pretty low in absolute numbers.

But wait. Isn't that the way ECL logic works?

[shabaz]

I can try that : ) I've stuck on some copper tape, then attached the following:
100pF 0402
10nF 0603
470nF 0805
I had to piggy-back the tant, due to lack of space. It is:
TPSD107K010R0050 (100uF).

Not sure what else to try on the current PCB. I could desolder the set of capacitors attached to the red wire, since there's now better decoupling on top of the chip.

Incidentally this circuit was dead-bugged before the PCB (photo attached), and the PCB version had improved rise- and fall-times. The dead-bugging was fairly tiny, the white wires were approximately the same length to each other in the photo.
 

[shapirus]

I can try that : ) I've stuck on some copper tape, then attached the following:
100pF 0402
10nF 0603
470nF 0805
I had to piggy-back the tant, due to lack of space. It is:
TPSD107K010R0050 (100uF).

And so it's now actually worse than it was with that tiny (what was it, 0805?) 1 nF cap attached with a piece of wire diagonally?

Interesting.

What if you try it again, but this time using the same copper tape instead of the wire?

[shabaz]

Hi,
I think there was an issue with the automated measurement on the 'scope, I've switched from 4nsec per division, to 1 nsec per division in that last post, to see it closer-up. i.e. it's not got worse, but no significant improvement either. I'll grab a cature at the 4nsec/div in case it helps to compare like-with-like, since I can't go back to the earlier layout without stripping off the copper tape etc. (EDIT: 4nsec-per-div rise capture now attached).

I've attached the top and bottom PCB layers (there's nothing on the underside apart from the ground plane). It's a 1.6 mm 2-layer board.

I'm looking for a deadbug version online to compare 'scope traces with, but so far I've only found a DIP package one in a YouTube video, so it's apples to oranges. I'll keep looking.

EDIT2: I've removed the superfluous capacitors at the C2 position, and directly wired the supply (red wire) to the tantalum cap, just in case it makes a difference. No significant difference in waveform quality unfortunately  (I can capture the 'scope trace if required, but it's near-identical to the previous one).

[shabaz]

I've looked around to see if there's any waveform examples for a dead-bug version of the project, and found this link: https://www.eevblog.com/forum/projects/compact-74ac14-pulse-generator-pcb/25/
There are several projects there. There's a PCB version using a cluster of single-gate 74AUC (I couldn't see which precise part), which achieves 410 ps. The waveform looks different, and it's running off a lower voltage, it's 1.5V p-p with a 50 ohm load.

[David Hess]

I am suspicious that nothing changed.  Could there be a problem with the test setup, like the cable connection to the oscilloscope?

Better pulse generators use a different type of circuit with current switching and parallel termination instead of voltage switching and series termination, and since the current is constant, the power supply is not disturbed when switching occurs.

That's quite interesting, but:

1) it assumes that the load impedance is constant, right? Not much of a problem, though, as they are typically designed to drive a 50 ohm load anyway.

A voltage source with a 50 ohm series termination is 50 ohms.  A current source with a 50 ohms parallel termination is also 50 ohms.  They appear identical from the outside.

2) it's terrible in terms of energy efficiency. But only in a relative way. In absolute numbers it's probably just fine, since, again, we only need to drive 50 ohm at a low voltage, so who cares if we consume two times the power, when it still stays pretty low in absolute numbers.

To generate the same output from a voltage source would require doubling the voltage, so the efficiency is the same.

If efficiency is required, for lower frequency applications a 50 ohm source can be synthesized from a lower value termination resistor and some positive feedback.

But wait. Isn't that the way ECL logic works?

It is exactly how ECL works, although ECL outputs are typically buffered with an emitter follower.  An ECL pulse generator output is typically buffered with a fast low capacitance diode, but it can also be buffered with a cascode transistor.

I have thought about using a fast CMOS output to drive a cascode transistor to make a current output, but it requires a bipolar supply voltage or virtual ground so not an easy modification for you.  I should build one on some copper clad board just to see what kind of performance various common transistor cascodes would provide.

[shabaz]

Unfortunately no, I think the cable connection is very good (I've tried two cables with the 'scope, with two BNC-to-SMA adapters at the 'scope end, just in case those had an issue). Both adapters are decent (from RS and not ancient), and one SMA cable is RG-316 from RS, and the other is RG-402 (self-soldered, but I take care with that, and use it with a VNA, no issues).
The right-angle connector on the board is cheap though (LCSC I think). I could try to unsolder it (hard!) and fit a better brand connector. EDIT: I'll dremel it off tomorrow and swap with a straight connector (in case those cheap right-angle ones are no good : ( I've not used those particular ones much).
I've tried swapping 'scopes, but it's a lower-bandwidth model (500 MHz) so I can't compare like-for-like : (

[shapirus]

A related question (since it's the same pulse generator that I'm talking about). What output voltage do I actually want? Need help choosing.

To answer this... There is nothing that prevents me from making it user-selectable! I'll simply add a jumper to switch between 5 (really ~4.7) V and 3.3 V, and the problem is solved. It will also allow to compare the rise times between the two, if I ever get access to a scope that has enough bandwidth for it.

[shabaz]

I hacked off the connector with a Dremel tool, and replaced with Amphenol 132322. There's a photo  showing the connection to the 'scope, it is using a SMA-to-BNC adapter (J01008A0017).
There are attached traces using channel 1, and channel 3 on the 'scope, to see if there's any difference, but they look the same. (channel inputs are set to the full BW, 1 GHz).

I could try a different voltage (the circuit operates from 3 to 5V, but I've been using a mains-to-DC 5V brick (I could attach to an adjustable PSU; might try that at some point).

[shapirus]

so... what decoupling cap arrangement resulted in the best rise time? :)
It was a bit hard to follow all the changes and results.

[shabaz]

Hi,
Overall with the capacitor mods, there was a few percent improvement in rise-time, especially with one or more capacitor(s) on top. The additional capacitors next to the chip, i.e. soldered on the PCB, improved rise time by a few picoseconds.
Scouring the web, it seems most of the 74AC based projects are reported to be in the 500-700ps ballpark.
There's lots of interesting things to try (for instance different packages, separating out the logic into single-gates devices, adjusting delays to smooth out the current demand, and so on), but it's diminishing returns if I stick with the current circuit and PCB and trying to make tweaks to it, since the circuit is already well within that ballpark.
It depends what performance you want. As is, it's already about tenfold faster switching compared to old boatanchor HP pulse generators (of which I own one, but it covers a large portion of desk depth whenever I want to use it, and it's noisy). Another interesting thing would be to attach your circuit to (say) Pi Pico (or whatever you're comfortable with) and then you've got the ability to program pulse trains (e.g. double pulse using the Pico PIO to make it very deterministic, or specific pulse widths and so on, depending on requirements).
 

[shapirus]

Hi,
Overall with the capacitor mods, there was a few percent improvement in rise-time, especially with one or more capacitor(s) on top. The additional capacitors next to the chip, i.e. soldered on the PCB, improved rise time by a few picoseconds.

I have just realized that placing the decoupling cap across the chip diagonally (for the shortest distance between VCC and GND) is not always what is actually required to improve the output rise time.

What is the output? It's a CMOS push-pull stage, isn't it? What path does the current take when the output switches to logic high?

Must be this (considering the short time in the vicinity of the event, so we can ignore the main power rails): decoupling cap positive -> VCC pin -> OUT pin -> source impedance matching series resistor -> output connector's center pin -> coax center wire -> load -> coax shield -> ground plane -> decoupling cap negative, and the loop is complete. This current does not flow via the IC's ground pin! Inside the IC it only flows from VCC to output via the upper transistor of the output stage.

Therefore, the decoupling cap must be placed with one terminal as close to the VCC pin as possible, and with the other terminal close to the *output* pin, and connected to ground there, as that's the spot where the return current will be flowing (it's effectively a high-frequency signal, so its return current follows the signal path where it can, which is on the ground plane right under the signal trace).

Am I wrong?

Now, of course there is also the IC's own current draw, which is required to drive the gates of the output stage, and this one must indeed be decoupled with a capacitor that's placed as close as possible to both the VCC *and* GND pins to provide a low-inductance path for that. So we ideally need two caps serving different purposes.

[David Hess]

Therefore, the decoupling cap must be placed with one terminal as close to the VCC pin as possible, and with the other terminal close to the *output* pin, and connected to ground there, as that's the spot where the return current will be flowing (it's effectively a high-frequency signal, so its return current follows the signal path where it can, which is on the ground plane right under the signal trace).

Am I wrong?

No, that is right, or close enough.  The decoupling should be between the IC's Vcc and the opposite side of the load which is the coaxial ground, and then also between the IC's Gnd and the opposite side of the load which is the coaxial ground.  In practice however this will be between the Vcc and Gnd pins in your case with ground plane construction.

[shapirus]

and then also between the IC's Gnd and the opposite side of the load which is the coaxial ground.

Did you mean to say between the IC's *VEE* (the negative rail, as in dual supply op amps) and the load's ground? That would make sense, of course, if we had a dual supply situation.

Decoupling between gnd and gnd, which have the same potential and are connected via a solid ground plane (and where we don't need to block DC), doesn't sound right.

[shapirus]

Now, for the capacitance values of the decoupling caps... The project is collecting dust in the kicad directory, because I can't decide on them lol. For one thing, by parallelling different value caps, say, 2 * 18 pF (for the 250-500 ps edge) + 1 * 22 uF (for everything else), one would expect to cover all the required switching frequencies with the lowest respective impedance of the caps. But:

1) parallelling different value caps can actually make things worse than using the same number of caps of the same value because of the parallel antiresonance effect, as explained in many articles (with references to simulation and measurements to prove the point);

2) I am not sure that the consideration of matching a particular SRF to a chip switching with a duration of the edge that roughly corresponds to that frequency is even applicable. Is it? It is, when we talk about filtering, and that's demonstrated in the IN -> filter -> OUT measurements. But does it work for the case of decoupling a switching node from the power delivery network, where we need the cap to provide a very high dI/dt via the lowest inductance path possible? It seems that the inductance of lower value caps (of the same physical size) is a little bit lower, for some reason, but not that much lower, the difference can be only 15-20% or so.

The best approach here would be "try both and measure", and I'd love to do that. But what do we do when a direct measurement is not feasible?

Right now I'm thinking of doing both at the same time: use a 15-18 pF cap or two between the driver's VCC and GND to provide the small but fast transient current required to power the gates of the output transistors of the IC, and a 22 uF cap or two (following the "use the highest value in a given package you can" advice) to power the actual output -- this however still has to be fast.

[David Hess]

and then also between the IC's Gnd and the opposite side of the load which is the coaxial ground.

Did you mean to say between the IC's *VEE* (the negative rail, as in dual supply op amps) and the load's ground? That would make sense, of course, if we had a dual supply situation.

Decoupling between gnd and gnd, which have the same potential and are connected via a solid ground plane (and where we don't need to block DC), doesn't sound right.

It doesn't matter if there is a direct connection between Vee and the load, as with a ground plane, but if that was not the case, then decoupling between them will improve the situation.  The idea is to reduce the loop area from both supplies to the load for the return currents.

A single supply by itself does not guarantee that one side has a low impedance connection to the load.

[David Hess]

Right now I'm thinking of doing both at the same time: use a 15-18 pF cap or two between the driver's VCC and GND to provide the small but fast transient current required to power the gates of the output transistors of the IC, and a 22 uF cap or two (following the "use the highest value in a given package you can" advice) to power the actual output -- this however still has to be fast.

The required decoupling capacitance can be calculated from the load capacitance and allowable voltage ripple, so driving an output capacitance of 10 picofarads with 1% supply ripple requires 1000 picofarads; the capacitances form a voltage divider.  Driving a bunch of unterminated transmission lines to other logic inputs with a quad or hex package can get into the 0.01uF range or sometimes higher pretty easily.

The ESR of the big bulk decoupling capacitor provides an AC termination for the power distribution network so it may only be located where the supply input is attached.  For local regulation this is provided by the regulator's output capacitor, but there might be some advantage to placing another one at the far end of the power distribution network.

[shapirus]

Finally built. Switchable 1024 kHz / 1 kHz frequency, switchable pulse width between 50% duty cycle and adjustable value from zero (or below what my scope can capture) to 100 ns. Switchable output (or rather the VCC level of the output drivers) 4.8V / 3.3V.



Need to whack a big electrolytic on the output of MIC5205, as there's ripple on the high level output voltage at 1 kHz, 50% duty cycle, and ~500 uF of total MLCC capacity on that rail doesn't fix it: it was fine with constant load, but it's not with pulsed load. (Yes I know that MIC5205 isn't supposed to be stable with ceramic caps)

The edges are for a separate topic :).