Building a pulse generator: puzzled by PCB trace impedance matching

[shapirus]

Every electronics hobbyist sooner or later decides that he must build his own fast edge pulse generator, and I am no exception.

I'm taking one of the easiest to reproduce routes: N fast logic gates (specifically 4 x SN74LVC1G04 SOT-23-5 inverters) having series resistors on their outputs whose values are chosen so as to provide, when connected in parallel, a specific (50 Ohm) source impedance.

High-frequency effects and the respective design considerations is mostly new field to me, so I have read a lot on this topic, but obviously much still remains to be learned.

When it comes to PCB trace impedance matching aimed at minimizing reflections, it seems to be generally accepted that it's not worth bothering with as long as the length of the signal trace (from the driver's output to the output connector's center pin) is short enough for the given operating frequency. Since we're talking about 400-500 ps rise/fall times for the ICs chosen, and the expected trace length will not exceed 1-2 cm, it seems to be the case here, too.

However I want to understand the general principle without taking the "the trace is short enough" shortcut.

Suppose we need to route an output signal trace that's long enough to consider its impedance. Let's also assume that all the resistors, ICs, and their input trace lengths are perfectly matched. We then have several layout possibilities:


A: connect all the resistors in the same spot right at their respective terminals and route a 50 Ohm trace from that spot to the output connector.




B: make individual traces, 200 Ohm impedance each, from each resistor, and join them at the center pin of the connector.




C: same as B, but make each trace's impedance 50 Ohm.




As far as I understand, there are two correct options: it should be A and one of B, C.

What is the correct one between B and C and why?



Now, part 2 of what I don't fully understand, somewhat related.

On one hand, we want to match the signal trace (effectively a transmission line) impedance to avoid discontinuity. With a 2-layer board with the bottom layer used as a solid ground plane reaching the 50 Ohm target requires that the track is made relatively wide: about 100 mils for a 1.5 mm FR4 board.

But on the other hand, increasing trace width also increases parasitic capacitance to ground that the driver will have to work against, potentially increasing the edge transition times.

It looks like we have a trade-off between matched impedance (to maintain signal integrity) and transition speed here.

Initially my idea was to remove copper on the bottom layer beneath the output signal trace and the area under the output connector to reduce the parasitic capacitance seen by the drivers, but now that I have read more on this stuff, in particular, the controlled trace impedance topic, I am no longer sure that it was a good idea.

Would like to hear what would the best approach in this case be, and why.

[tggzzz]

C's impedance at the socket is 50//50//50//50 = 12.5ohms, whereas A and B are correct. I've used variant A with success, assuming the 74LVG gate output impedance is about 7ohms, and paying very careful attention to decoupling.

Where a track is acting as a transmission line, considering its capacitance alone is wrong. You have to consider both capacitance and inductance, and that leads (ho ho) to the characteristic impedance.

The characteristic impedance of a line depends on the other nearby conductors. Keywords: stripline, microstrip, coplanar waveguide, plus their differential variants.

The various online calculators will give a hint about the the relevant dimensions.

[shapirus]

C's impedance at the socket is 50//50//50//50 = 12.5ohms, whereas A and B are correct.

That's what I thought, but since transmission lines are special, I wasn't fully convinced about how characteristic impedance works when they are joined like this.

I've used variant A with success, assuming the 74LVG gate output impedance is about 7ohms, and paying very careful attention to decoupling.

I have actually measured output impedance, or, actually DC resistance (HF scenario may be different, and I'll have to test that later as well) at about 12 Ohms, using 150, 200, and 300 Ohm resistor as load at VCC=3.3 V. It's TI's SN74LVC1G04DBV, should be an original part. Conveniently, I have some 187 Ohm 0805 resistors that will suit the 4x topology.

Where a track is acting as a transmission line, considering its capacitance alone is wrong. You have to consider both capacitance and inductance, and that leads (ho ho) to the characteristic impedance.

Yeah, parasitic inductance is what I overlooked. But... Consider a super-wide signal trace, for low inductance, then no copper on the bottom layer for low capacitance... Since Z = sqrt(L/C), we can retain the same Z while decreasing both L and C by the same factor. Apparently this is what effectively takes place as the diameter of coax cables is increased to reduce losses, while maintaining the same characteristic impedance.

The characteristic impedance of a line depends on the other nearby conductors. Keywords: stripline, microstrip, coplanar waveguide, plus their differential variants.

It was after reading (and watching) on this topic that some questions were answered, but even more questions arised .

The various online calculators will give a hint about the the relevant dimensions.

Yeah, and there's actually a nice calculator in Kicad which I'm using. I wonder if it can calculate the trace on the fly as it's laid out in the PCB editor. It probably can't, but I haven't looked into it closely yet.

[newbrain]

I have actually measured output impedance, or, actually DC resistance (HF scenario may be different, and I'll have to test that later as well) at about 12 Ohms, using 150, 200, and 300 Ohm resistor as load at VCC=3.3 V. It's TI's SN74LVC1G04DBV

If you head to the TI page for the 74LVC1G04, you can find it's IBIS model.
It's a series of tables that give the dependency between output current and voltage under different conditions (e.g. different supply voltages) and the rising and falling waveforms.
The (linear regression) of the V/I slope can be considered a decent approximation of the output impedance.

[shapirus]

If you head to the TI page for the 74LVC1G04, you can find it's IBIS model.
It's a series of tables that give the dependency between output current and voltage under different conditions (e.g. different supply voltages) and the rising and falling waveforms.
The (linear regression) of the V/I slope can be considered a decent approximation of the output impedance.

There's quite a spread between min and max values. It's ok for rough estimation, but I'll better measure the actual parts I have at hand myself -- this will also help to see how closely (or otherwise) matched they are, at least in terms of output resistance.

[tggzzz]

I've used variant A with success, assuming the 74LVG gate output impedance is about 7ohms, and paying very careful attention to decoupling.

I have actually measured output impedance, or, actually DC resistance (HF scenario may be different, and I'll have to test that later as well) at about 12 Ohms, using 150, 200, and 300 Ohm resistor as load at VCC=3.3 V. It's TI's SN74LVC1G04DBV, should be an original part. Conveniently, I have some 187 Ohm 0805 resistors that will suit the 4x topology.

I wouldn't argue with that value, and the IBIS files seem to confirm it is higher than 7ohms. (I hadn't seen the IBIS information when I made my edge generator).

Ultimately you might end up twiddling resistors to see which is best in practice.

Interestingly, if I understand the IBIS file's contents, it looks like the risetime is pretty much what I've crudely measured, i.e 260-300ps.

Where a track is acting as a transmission line, considering its capacitance alone is wrong. You have to consider both capacitance and inductance, and that leads (ho ho) to the characteristic impedance.

Yeah, parasitic inductance is what I overlooked. But... Consider a super-wide signal trace, for low inductance, then no copper on the bottom layer for low capacitance... Since Z = sqrt(L/C), we can retain the same Z while decreasing both L and C by the same factor. Apparently this is what effectively takes place as the diameter of coax cables is increased to reduce losses, while maintaining the same characteristic impedance.

I'm just trying to think if there's any room for improvement, if we talk about the PCB layout, over the classic microstrip with a trace width calculated to have a 50 Ohm impedance. That's of course after the traces are made as short as possible already.

The characteristic impedance of a line depends on the other nearby conductors. Keywords: stripline, microstrip, coplanar waveguide, plus their differential variants.

It was after reading (and watching) on this topic that some questions were answered, but even more questions arised .

The various online calculators will give a hint about the the relevant dimensions.

Yeah, and there's actually a nice calculator in Kicad which I'm using. I wonder if it can calculate the trace on the fly as it's laid out in the PCB editor. It probably can't, but I haven't looked into it closely yet.

The calculators are all approximations, of varying validity.

Have a look at coplanar waveguide and microstrip, and compare the sensitivity to changes in dielectric constant and thickness, and track/gap dimensions. Horizontal spacing is much better controlled than thickness and dielectric constant.

Then have a look at microwave stripline filters

[shapirus]

HF scenario may be different, and I'll have to test that later as well

It is. Not much, in absolute values, but at VCC=3.3V, when sourcing current into a 200-Ohm load, the ...1G04 has (have: they are quite nicely matched indeed, within ~2% at DC, much of which may be caused by the measurement error) frequency-dependent output resistance: from ~12.5 Ohm at DC to 13.6 Ohm at 5 MHz, 16.8 Ohm at 16 MHz and 20 Ohm at 20 MHz.

However, this may very well be the effect of the parasitic inductance of connections, and now that I'm writing this, I really think that it's the major contributor. The chips I tested were installed in a SOT-23 ZIF socket with certainly more than negligible length of contacts, legs and traces of the breakout board. These few added ohms can very well be attributed to them.

But it doesn't really matter too much in any case. Relative to the the ~190 Ohm series resistance on the output of each gate these few extra ohms will mean almost nothing in practice.

[tggzzz]

(Wrong attribution for the HF scenario!)

A secondary effect of lead inductance is that the L^di/_dt can reduce the drive to the output transistors, thus increasing the transition time. That can look like extra increased resistance.

One advantage of paralleling the driver+resistor is that it reduces such effects and allows each output to switch a little faster.

In the end there is some degree of suck-it-and-see.

[shapirus]

A related question (since it's the same pulse generator that I'm talking about). What output voltage do I actually want? Need help choosing.

Input power will be USB 5 V. Thus I can do e.g. 3.3 V or, say, 4.7 V, where the 0.3 V difference will drop on the LDO linear regulator (might go a bit higher, as the LDO still allows that, but I want to have that extra margin for poorer input say 4.9 V etc.).

- 5 V output makes it a bit more tricky to lay out the board well. In any case I will have the 3.3 V rail to power the oscillator part, which starts to consume increasingly (disproportionally) more power at 4+ V, and that includes the crystal drive level, so I want to stick with no more than 3.3 V for that part, whereas the output driver part can be powered by up to 5 V no problem. So with 3.3 V output I will need to route just one power rail, and two with 5 V; and that's on a 2-layer board.

- 3.3 V-powered driver potentially means a shorter output rise time, because it is probably limited by the output stage's slew rate: thinking it may simply take more time to go from zero to 3.3 V than from zero to 5 V.

- on the other hand, the output driver (74LVC) may be faster at 5 V, which is definitely the case for propagation delays, but it's not the propagation time I'm after, but the transition time -- will it be affected by the supply voltage? The datasheets are silent about this.

- any other considerations to prefer one over the other? Right now I'm building this pulser just out of curiosity to explore the behavior of the oscilloscope, to watch reflections in cables, compare different probes against each other and a 50 Ohm cable connection, etc., and these applications don't require any particular signal level: all they care about is the transition times and the pulse length. Maybe there is some specific application for such a pulser that I'm not thinking about at the moment that would warrant going for the (almost) 5 V output?

[tggzzz]

See https://www.eevblog.com/forum/testgear/show-us-your-square-wave/msg1902941/#msg1902941

If you have a 5V PSU and 50ohm matched impedance, you will only get 2.5V into scope.

That circuit works below 1.5V (use a bench PSU), but with "noticably" increased risetimes

Make sure layout and decoupling is very good; di/dt of 50mA/250ps interacts with L

Why are you using a crystal oscillator if you are only interested in the risetime? Just use the standard R+C+schmitt relaxation oscillator.

[jonpaul]

https://www.leobodnar.com/shop/index.php?main_page=product_info&products_id=295

40 pS.

Direct to BNC for scope.

USB power

Jon

[shapirus]

See https://www.eevblog.com/forum/testgear/show-us-your-square-wave/msg1902941/#msg1902941

If you have a 5V PSU and 50ohm matched impedance, you will only get 2.5V into scope.

Yeah I've seen that post. Of course the voltage seen by the scope is divided accordingly.
Quite impressive rise times for an off the shelf dirt cheap logic gate -- that's why I decided to go this way.

BTW, as a side note, speaking of off the shelf parts, here's what I was able to achieve in my previous pulser that was not aimed at particularly fast transition times, but was intended to produce pulses of adjustable length, amplitude, and frequency: 60 ns to (iirc) 15 us, 3 V to 12 V (before the 50 ohm source series resistor), 1 Hz to 110 Hz.

Output is a push-pull BJT complementary pair -- and no fancy transistors here -- as a matter of fact, it's the TO-126 (!) cheap noname "X values 10 pcs each kit" stuff from aliexpress.

Here it is connected to the scope via the shortest path possible, a BNC male to male adapter and a feed-through 50 ohm terminator:

1. Max amplitude




2. Min amplitude




Not bad at all for this kind of output stage, I would say.

That circuit works below 1.5V (use a bench PSU), but with "noticably" increased risetimes

Interesting. Do you remember (or can you check) if the transition times increase linearly as the supply voltage is lowered, or there's any sweet spot in the middle? This may make going for 5 V worthwhile.

Make sure layout and decoupling is very good; di/dt of 50mA/250ps interacts with L

Yeah, decoupling is yet another rabbit hole. I'm now researching this topic to understand what/how is the best I can do with a 2-layer board, hand soldering, and 0805 parts (of course, no doubt, after the board layout is already done -- but redoing the caps is easy enough). Could go with 0603, perhaps, but hey, that's already at the edge of staying within reason for a DIY board. It's not THAT critical, just want to achieve a reasonable maximum with what I have and can do.

Why are you using a crystal oscillator if you are only interested in the risetime? Just use the standard R+C+schmitt relaxation oscillator.

Just for the heck of it, basically. For one thing, this is an opportunity for me to play with a crystal oscillator and see how it behaves. And now that I've built a decent one, why not use it, especially given that I have enough space for it on the board? Never hurts to have a stable (and also I'll make it user adjustable) repetition rate with low(ish) jitter.

[shapirus]

https://www.leobodnar.com/shop/index.php?main_page=product_info&products_id=295

Of course I know about Leo Bodnar's pulser. But I want to build a pulser, not buy one. I could repeat the design, but for a number of reasons I'm going with a different output stage driver for now.

[shabaz]

Just for ideas, the photo below shows my basic fast-edge generator (it generates approx square waves, with a switch to select 0.1/1/10 MHz). It's not brilliant, so you probably won't want to directly copy it, but maybe there are ideas to rule in or rule out.
I just kept the signal traces as short as I could, there's not much length to the transmission lines, and it's not very well designed, I think I've got around 120 ohm characteristic impedance with the trace width. I used 200 ohm resistors, they have not been optimized, although I would have liked to work on it further at some point.

In terms of performance, I see 480 ps rise, and 420 ps fall times. This was with an On Semi MC74AC02DG (bought from a distributor, so I know for sure that's the part and mnfr that was used).

If I was going to do it again, I'd make these changes:
1. Maybe try to guesstimate the lead length differences for the signals inside the SOIC chip to compensate a bit for that (or use a smaller part)
2. Improve the transmission line characteristic impedance
3. Maybe not use the LTC1799 because it's expensive for what it is
4. Maybe add another switch for an additional few frequencies inside each decade
5. Although it works at 3-5V, maybe add a USB connector for power instead of the barrel socket, and have a 3.3V regulator that can be bypassed with a switch, so that both 3.3V and 5V outputs are easy to select
Other than that, I was generally OK with it, obviously, it's nowhere near state-of-the-art rise/fall times, but still handy from time to time (and I really didn't want to spend £100+ on a ready-made pulse generator that I would rarely use).

[metebalci]

On one hand, we want to match the signal trace (effectively a transmission line) impedance to avoid discontinuity. With a 2-layer board with the bottom layer used as a solid ground plane reaching the 50 Ohm target requires that the track is made relatively wide: about 100 mils for a 1.5 mm FR4 board.

Avoiding a 4 layer board on purpose ?

[Mahagam]

Only one 100n capacitor (C2) is not enough. Perhaps this is the reason why falling edge faster than rising.

[David Hess]

In terms of performance, I see 480 ps rise, and 420 ps fall times. This was with an On Semi MC74AC02DG (bought from a distributor, so I know for sure that's the part and mnfr that was used).

Where is the 250 MHz ringing coming from?  My guess is insufficient decoupling of the MC74AC02DG.

Where is the preshoot coming from?  It starts too early for it to be from the inputs of the MC74AC02DG.  This might also be caused by insufficient decoupling of the MC74AC02DG if power is sagging from earlier in the circuit.

When the MC74AC02DG switches, it connects its outputs to either Vcc or Gnd, which extends the transmission line length from its outputs through Vcc or Gnd.  Decoupling of a power stage requires a lot more capacitance and lower impedance.

[shabaz]

That 100nF had been on my mind too. I've added two capacitors to it (100pF alongside it, and then a 10uF 25V X5R on top).
It has improved the risetime very slightly (not much unfortunately).
Maybe it still needs a lot more capacitance I'll dig around for a 22u X7R and add that instead of the 10uF.

I've attached a render of the entire PCB, the derivation of the supply from the C1 instead of directly from C3 was a bit naughty too, but that's easily fixed by cutting the trace and connecting a jumper wire more directly.

Not sure what else to try on the current board layout unfortunately : (

[shapirus]

Avoiding a 4 layer board on purpose ?

Sort of. For a homemade board, 4 layers is just not viable, and if I order at a fab house, then, even though the price increase compared to 2-layer isn't too high, the shipping time of at least three weeks (no direct airmail now, everything goes via transit countries) is going to kill all the fun. So I'm going the homemade route. Besides, I would first want to build a prototype anyway, and once a prototype is ready and working, I would hardly need to have another copy.

Two layers are actually almost fine. Yes I had to make holes in the ground plane here and there, and route a couple of traces, but there are no splits where it would matter, and I did pay attention to how the return currents, per my understanding, will flow, and avoided creating any ground plane discontinuity there.

[shapirus]

Maybe it still needs a lot more capacitance I'll dig around for a 22u X7R and add that instead of the 10uF.

You don't need capacitance, instead you need to minimize inductance. Some good food for thought and visual demonstration of switching effects can be found here:



It doesn't answer all the questions though, but still that's a good one.

Not so long ago someone on this forum suggested a clever trick of using a small (e.g. 0603 or 0402 depending on your PCB) capacitor inside a non-plated hole, one end being right at the VCC pin, another soldered to the ground plane. This makes the inductance loop one via length shorter :).

There are also low-inductance side-terminated capacitors, see https://www.montana.edu/aolson/ee433/caphfmodel_ieee.pdf. Useful when you really need to squeeze out every last bit of the parasitic inductance.

[shabaz]

I think you're right. I had hoped that the multiple via-holes around the capacitors would have helped, but such pulse generators need a lot more consideration.
I took the decoupling a lot more seriously in the photo below, with 100nF+100pF, flanked by two 10uF X7R capacitors. Also changed the far-away capacitor to a 220uF electrolytic, and wired it directly. And finally added a 1nF capacitor using that diagonal wire over the chip, to try to reduce inductance in at least some of the decoupling. I gained a few picosecond improvements here and there, but actually that last capacitor made most difference; the rise-time has improved a reasonable amount.
It's probably diminishing returns at this point, unless a better package was used other than SOIC to help reduce inductance. It might improve the shape too, since there could be interactions due to discrepancies in length of signals due to the SOIC package, which I didn't take into account.

[metebalci]

I took the decoupling a lot more seriously in the photo below, with 100nF+100pF, flanked by two 10uF X7R capacitors.

My understanding is with SMDs using smaller values for decoupling is not important. Because all has similar inductance. If you can go for a smaller package ok but otherwise the best is to use a single large value (or two same values etc.).

Edit: also you can use a wider trace from decoupling cap to IC and gnd vias.

[shapirus]

My understanding is with SMDs using smaller values for decoupling is not important. Because all has similar inductance.

Well, sort of, yes, if we're speaking about the inherent inductance of the package, but then, let's look at the impedance vs frequency graphs, which very clearly indicate the difference in... let's call it, apparent inductance.

For example, for cap values from 100 pF to 10 uF in x10 steps, all in the 0805 package:



(https://ds.murata.co.jp/simsurfing/mlcc.html)

If this characteristic is applicable for determining the bypass capacitor values, then for each given frequency there will be a specific capacitor with the lowest impedance that will work best.

If I understand it correctly, then, say, 500 ps rise time roughly corresponds to ~1 GHz frequency, and so the best decoupling cap to serve the transition edge would be one with the impedance notch at this frequency. It must, at the same time, store enough charge to provide the required current during the transition until the "slower" bulk capacitors catch up and begin providing power at the high level of the pulse.

This is where the idea of parallelling several capacitors of different values comes from. It doesn't however, always work as expected: see Dave's video:



also see https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values (I have yet to read this one -- it's opened but waiting).

[metebalci]

also see https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values (I have yet to read this one -- it's opened but waiting).

This would also be my source for the info, from Eric Bogatin's book I believe I read the last time

[tggzzz]

That circuit works below 1.5V (use a bench PSU), but with "noticably" increased risetimes

Interesting. Do you remember (or can you check) if the transition times increase linearly as the supply voltage is lowered, or there's any sweet spot in the middle? This may make going for 5 V worthwhile.

Higher voltage => faster. It is because you are driving the (internal) transistors harder with higher currents.

Make sure layout and decoupling is very good; di/dt of 50mA/250ps interacts with L

Yeah, decoupling is yet another rabbit hole. I'm now researching this topic to understand what/how is the best I can do with a 2-layer board, hand soldering, and 0805 parts (of course, no doubt, after the board layout is already done -- but redoing the caps is easy enough). Could go with 0603, perhaps, but hey, that's already at the edge of staying within reason for a DIY board. It's not THAT critical, just want to achieve a reasonable maximum with what I have and can do.

Poor decoupling can lead to a poorer waveshape; that's the principal reason for ensuring it is as good as possible.

Two points: 0306 would be better than 0603, and watch out for the capacitor's value when it has 5V across it. You can "lose" >80% of the capacitance that way, so check the specs

I'm considering re-spinning the board on 4 layers, just for the hell of it and to learn KiCAD. But first I want to understand how solid Vcc/Gnd planes resonate, and how to damp that.

There are lots of things I want to do