Calculating Op-Amp Stability Driving Capacitive Loads

[wigman27]

Hi all,

I know there has been quite a bit of discussion about this issue on the forum but I was hoping to have some help please on calculating "ideal" values for compensation resistors with a specific circuit and example so that I can apply it in the future.

I am hoping to drive a BUK954R8-60E MOSFET (datasheet) with an AD8628 op-amp (datasheet)

What I have so far,

• That the op amp is stable at unity gain
• A - The open loop gain Vs frequency of the op-amp(image below)
• That Axß cannot equal -1 or have a 180 degree phase shift above the 0dß line or have a -40dß slope per decade through the 0ß line. (all in the same thing I'm guessing)
• That I think the output resistance of the op-amp is 100 ohms, is this correct? Calculated from the impedance VS frequency graph at the GBP

What I would really appreciate help with is,

• determining if my equivalent circuit is correct
• If I have read the datasheet correctly and found that the gate capacitance is a max of 9710pF so I have used 10nF for ease.
• How to figure out the frequency of the second pole that will cause a -40dß slope, then the third pole that will bring it back to -20dß slope so I can create the ß graph and multiply it to the A graph of the opamp.
• How then to calculate the values of the compensating components and how best to place them

I'm really sorry about the complexity of this question however I will certainly benefit from it and I hope others will to

Thanks

Lee

[Jay_Diddy_B]

Lee,

Can you post your schematic?

I assume that you aiming on high accuracy if you are using a chopper stabilized op-amp for the current measurement. Can you post a summary of the specifications that you are aiming for?

The SOA graph for the MOSFET shows that it is capable of 100W dissipation at 1V, but this will probably be limited to 40W by the heatsink. At 60V this is reduced to 20W by the SOA curve.

Regards,

Jay_Diddy_B

[wigman27]

Hi Jay_Diddy_B,

Great to see you again

I am really sorry about that, They must have not uploaded correctly. I have edited the original post and they are there now.

My original Rev b schematic is here. But I will be replacing the LM324 with an AD8630 and removing those 100n caps from the buffers (who know what I was thinking).

The specs for rev b are

Maximum Input Load Voltage - 24V
Maximum Input Load Current - 8A
Maximum Input Power Dissapation - 50W
Operating Voltage - 5V
Power Source - USB or External Power Pack (5V)
Minimum load current draw - 15mA - Due to op-amp offset. (hoping to minimise this)
Load Current error - Up to Approximately 3mA.(hoping to minimise this also)

Thanks again

Lee

[Jay_Diddy_B]

Lee and the group,

I posted my analysis of this type of circuit in this thread:

https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg462562/#msg462562

I will have to think what changes are required for the NXP MOSFET and the AD8630 op-amp.

It is going to be a balancing act between power dissipation in the sense resistor causing self-heating and drift versus offset voltage and signal level at the low end.

Regards,

Jay_Diddy_B

[wigman27]

Thanks Very much Jay_Diddy_B,

That was very explanatory and well described however I still found it a little difficult to follow when it came to replacing the components with their internal equivalent. I feel I would stuff this up on my first attempt.

I have watched video from LT spice on how to plot the open loop gain of an Opamp using LTspice. I have tried my best to use this information and apply it to my non-inverting application. I hope I have this correct.

An image of my test circuit is attached below (Sorry I'm not sure how to put attachments in line)

This is the uncompensated version and shows the following results.

Has a -20dß slope at the 0db crossing and a phase of 29.47º. This would suggest that it is stable (which I was quite surprised with) but only just. This would appear correct because when tested with a trans response the uncompensated circuit appears stable.

I then tried to add a gate resistor (to improve the phase margin) and steped values from 1R in orders of magnitude to 1000R, and again to my surprise this actually made the response worse and in some cases made it unstable.

So I added a series resistor in the feed back path of 1k like the original circuit and tried again, this improved things, so I added the gate resistor again and it improved it even more so I tried adding the capacitor between the gate and feed back path and improved it even more so I continued playing with values until I came up with the final circuit which has a phase of 83.73º and an approximate -20dß slope at 0dß. To my inexperienced eye that appears to be quite good.

So I did a trans test again with the final results appearing positive with a slight under damped response for the full load current but reaches steady state within approximately 4µs.

I hope I have done this correctly, any feed back would be fantastic (pardon the pun)! It appears quite good on paper.

Thanks

Lee

[dannyf]

Depending on the mosfets used, I would put a small resistor on the opamp's output. I would start at 220ohm and work my way down from there.

[T3sl4co1l]

Based only on small-signal parameters, it's not possible to determine if an op-amp will be unstable with a given load.  Some will be unstable due to hidden characteristics of the output stage itself, which will not show up on that type of analysis.

The safest way to design this type of circuit is to isolate the op-amp with series resistors, and add a compensation C or R+C network from out to -in.

Tim

[Zero999]

Is VLoad always going to be a stable 24V or could it be something like an inductor?

If VLoad is always a low resistance, it should be fairly stable because the feedback is taken from the MOSFET source so there's negative feedback to reduce the gate impedance seen by the op-amp.

[Jay_Diddy_B]

Hi Lee and the group,

I have repeated the analysis that I originally performed in this thread:

https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg462562/#msg462562

Using the components that were chosen by wigman27.

This is the progression of the analysis.

First I made a simplified model of the BUK954R8-60E MOSFET so that I could explore the small-signal behaviour. The small signal model does not include the gate threshold voltage Vgs. Ciss and Crss were obtained directly from the NXP datasheet. The transconductance of the MOSFET was determined from the slope of the transfer function. The current changes by 15A for 0.25V change in Vgs giving Gm=60.



AC Analysis of the MOSFET output stage:




I then added some lead inductance and resistance, this is to model the wiring between the load and the power supply under test. It is very important to include this in the model (as we will see by the results).



AC Analysis with wiring inductance and resistance.




You can see the resonance that was created when the inductance was added.


A damping circuit (snubber) was added to suppress the resonance:





The results show that the damping circuit is an effective counter measure.


I now placed the AD8630 in a test circuit to confirm the correct operation of the model:



The op-amp test gave reasonable results.




Complete control loop

I then added the op-amp circuit and the MOSFET circuit together to make the complete control loop:



These are the results using the component values proposed by wigman27:



Although the control loop is stable, the phase margin is too small.


I increased R3 from 100 Ohms to 270 Ohms to reduce the gain and increase the phase margin.



The result is a very acceptable control loop.



To be continued..

Regards,

Jay_Diddy_B

[Jay_Diddy_B]

To look at the op amp stability, I moved the test source the op amp's input.



The results show the op-amp's feedback loop is stable:



This is a model that has been tested on similar hardware and given results. There is no substitute for bench testing.

Jay_Diddy_B

[wigman27]

Thank you SO VERY MUCH!

I am so sorry this has taken me so long to get back to you, Work has been stupidly busy, Uni has been busy, family not been well and my dearly beloved wanted a new kitchen installed... So My electronics have taken a pause! But.. I'm back!

I have recreated every step you have shown me with quite a lot of success! Thank you I will use the components you have suggested and test on the breadboard.

I just have a few questions when it comes to testing the opamp in a buffer condition driving a capacitive load. The reason I am asking is I would like to simulate what the opamp will do when buffering into an my ADC MCP3204 (datasheet). The datasheet for the opamp kindly has graphs that show a phase margin of 52.6 deg when driving a 20pF load, which is the exact input capacitance of my ADC, however the datasheet also shows a pin capacitance of up to 10pF and I was curious what the phase margin was with this added.

I have tried many different things but just can't come up with a way to simulate the op-amp in a buffered condition.

Also, 1 more question please,

Hi Lee and the group,

I now placed the AD8630 in a test circuit to confirm the correct operation of the model:



The op-amp test gave reasonable results.

Where did this circuit come from? Is this s standard circuit you use to test subckts?

Thanks again mate, I really appreciate it!

[Jay_Diddy_B]

Also, 1 more question please,

Hi Lee and the group,

I now placed the AD8630 in a test circuit to confirm the correct operation of the model:



The op-amp test gave reasonable results.

Where did this circuit come from? Is this s standard circuit you use to test subckts?

Thanks again mate, I really appreciate it!

The test circuit is a standard op-amp circuit, with R2 added. The purpose of R2 is to limit the DC gain of the circuit. Without R2, the op-amp will integrate the input, until the output saturates at either of the two rails.

Without R2, the circuit is an integrator, it should have 90 degrees of phase shift and the 0dB, unity gain should be at a frequency:

1 / 2 x PI x R1 x C1  = 159 kHz.

The deviation from 90 degrees at high frequencies comes from Gain Bandwidth product of the op-amp.

The deviation from 90 degrees at low frequencies comes from R2 limiting the DC gain.

You can see that the characteristics of the circuit are dominated by the passive components, not the op-amp. This is a good thing. It means the circuit will be tolerant of variations in the op-amp specification.

Regards,

Jay_Diddy_B

[wigman27]

That makes perfect sense! Thanks mate ;-)

I am about to do liner systems at uni and it's good to apply this to the subject! It's a bit full on this subject.

Sorry to keep asking so many questions, are you able to show me a way to model op-amps as a buffer to feed into the adc?

Thanks again mate!

Lee