high speed PCB design, when to consider?

[bogdant]

I am designing a custom board with stm32h735 that use
https://ro.farnell.com/stmicroelectronics/stm32h735zgt6/mcu-32bit-550mhz-lqfp-144/dp/3576967
 - external USB PYH USB3300
https://ro.farnell.com/microchip/usb3300-ezk/ic-usb-2-0-ulpi-phy-w-otg-32vqfn/dp/2292614
 - external RAM
https://ro.farnell.com/cypress-semiconductor/s27kl0641dabhi023/dram-64mbit-36ns-fbga-24/dp/2749800
- SD connector
Does it make sense to apply High speed PCB design, topics like matched length trace, differential pair signals..?

[tggzzz]

Read the data sheets and application notes for the devices you are using.

For digital circuits understand that the period/frequency of a signal is completely irrelevant. The only parameter of interest is the rise/fall time. See, for example, https://entertaininghacks.wordpress.com/2018/05/08/digital-signal-integrity-and-bandwidth-signals-risetime-is-important-period-is-irrelevant/

Make sure there is adequate decoupling and a ground plane.

Bogatin gives a lot of useful information at https://www.edn.com/bogatins-rules-of-thumb/

[Berni]

It depends on the application

In general doing things like length matching and avoiding sharp corners with smooth curvy traces and such is not needed. The only important thing is to run differential traces as proper differential pairs, not doing this can really mess up the signal.

So for things like SRAM, SDRAM, SD cards etc it doesn't really matter how you route them, as long as you don't have one trace doing 4 laps around the whole board before connecting to where it goes. As long as you have a good solid ground plane those signals are fine.

As interfaces get faster then you might want it. For example anything with DDR memory is a good idea to length match because transferring data on both clock edges makes timing requirements a lot tighter and they generally run at rather high clock speeds.

[bogdant]

I found this online course about altium pcb advanced topics :
https://academy.fedevel.com/courses/online-advanced-pcb-layout-course
Did anybody know if the content is what I need? Did you try this course?

[KB1LQC]

Keep your life easy. Remember the golden rules of good PCB design (IMHO):

• Current returns directly under the routed trace at high frequency
• Never break the ground plane below a referenced signal

Obviously that's very simplified but it will go a LONG way. I suggest using lumped element routing keeping as much as reasonably possible less than the length where impedance matching matters. On traces where this may be an issue use impedance control and if that's not possible ($$$) then at least design a specific impedance and terminate it but you may get away without having the fabricator control the impedance. Lastly, decoupling is your friend.

Unless the datasheet states to length match you probably don't need it. The difference in difficulty between "good enough" and "perfect" high speed layout can be dramatically high!

[Rerouter]

Its always good to keep in mind, its more a scale of how much you want to prioritise it,

For this project the critical signals like RAM and the USB PHY I would say yes, The SD card comes down to your max read rate,

Match only to what the specs require + some margin, if you can go better then fine, but too many get caught up on 0.001mm when the spec was 2mm length matching,
Make sure high speed signals have an unbroken ground path, you can jump layers with vias but you need a via for the ground aswell then, path of least impedance rules here, either below or beside,
Ground via placement kind of follows the above, make sure the path to the chips ground plane is convenient for the signals,
Keep decoupling caps close to the load, and make them connect to the capacitor and the supply on different traces if possible

I personally stop caring about impedance below smallest wavelength / 20 length traces,

[schratterulrich]

We use a similar setting on many boards with STM32H7 and USB3300 in the company I work for.
STM32H7 signals have very fast edges with low output impedance. I would strongly recommend series termination resistors. And then you will need impedance controlled traces, too.
Without them you will easily get reflections that are higher than your absolute maximum ratings in your datasheets. And you can't always use slower GPIO settings, as your datasheet may tell you to set the fastest speed settings for external RAM and ULPI. Or at least the timing is valid for the fastest setting only.
I remember, that the USB3300 or similar in combination with a STM32F7 results in a very tight timing budget and the datasheet numbers would give you 0ns!! hold time. 
The STM32H7 is faster and a little bit better I think.
I wouldn't give away too much reserves by not length match the traces for the USB3300.

It is definitely high-speed design.

[bogdant]

For the ULPI and external RAM I have the length match traces with 1mm tolerance. Here you can find the output from Altium project
https://github.com/bogdan-tirzioru/BusAnalizer/tree/master/layout/busanalizer/Project%20Outputs%20for%20BusAnalizer
It is my first 4 layer design. 2 layer signal and GND and VCC internal layers.
Also the USB lines to connector there are differential routed.

[bogdant]

What is a "lumped element routing" ?
Related to datasheets, in the USB3000 there is only for output differential pair:
 - differential rise time Thsr = 500ps
 - differential fall time Thsf = 500ps (page 14)
There is only for ULPI interface following timing:
 - Setup time Tsc,Tsd = 5ns
 - hold time 0 ns
 - output delay Tdc, Tdd= 2ns(min) (page 19)
https://github.com/bogdan-tirzioru/BusAnalizer/blob/master/AN/USB3300-00001783A-468119.pdf
On the microcontroller side stm32H735 I found following timing (page 241)
 - Control in setup time Tsc = 5ns (min)
 - Control in hold time Thc = 0ns
 - data setup time Tsd= 2.5ns
 - data in hold time Thd = 0ns
 - control/data output delay Tdc/tdd = 6ns (max 8ns)
 https://github.com/bogdan-tirzioru/BusAnalizer/blob/master/AN/735/stm32h735zg.pdf
Where can I find the tolerance of length traces for USB or how to calculate it? 

[tszaboo]

Read the data sheets and application notes for the devices you are using.

For digital circuits understand that the period/frequency of a signal is completely irrelevant. The only parameter of interest is the rise/fall time. See, for example, https://entertaininghacks.wordpress.com/2018/05/08/digital-signal-integrity-and-bandwidth-signals-risetime-is-important-period-is-irrelevant/

Make sure there is adequate decoupling and a ground plane.

Bogatin gives a lot of useful information at https://www.edn.com/bogatins-rules-of-thumb/

Pretty much, read the datasheet and application notes.
DDR1 RAM for example, doesnt look that high speed, you can run it at lower frequency, like 50-60MHz, so it should be easy, right? And then you realize that some clock signals should go high within a few ps from each other.
I've seen a manager, writing FPGA code, then connecting a 1 GHz oscilloscope with passive probes to the DDR interface, trying to debug it.
Hint: high speed without experience and tools is not fun.

[bogdant]

The experience is gain by doing and study, and most of the time by failing.
What kind of equipment you meant in previous post?

[Berni]

This gets into low loading active probes and >4GHz scopes to properly see fast DDR RAM signals.

But for things like SDRAM and ULPI its not really that critical. Just lay it out like they tell you, or look at how one of the dev boards did it and it will run fine.

I did things like run 700Mbit serial signals over a ribbon cable cut off from a old floppy cable. Works just fine as long as there is a good ground return path.

[tszaboo]

The experience is gain by doing and study, and most of the time by failing.
What kind of equipment you meant in previous post?

Best equipment for it is of course a fast scope. Active scope probes are essential. You want to keep the loading of the probe minimal, and it has to be fast, as Berni said. For some signals, you might get away by soldering a 1K resistor on the line, and then using the 50 Ohm input of the scope (with an SMA to BNC cable for example), but that's the exception, not the rule.
Then you might need, depending on the issue and the speeds, BERT, Near field probes with a spectrum analyzer, protocol analyzers, test fixtures that cost more than other people oscilloscopes. All these are costly.
In the end there is a difference between a working system, and a properly designed and tested system. Few people will understand this, most will say: I soldered it together and it is blinking an LED, so must be good.

[BitsnBytes]

It is always a good practice to follow the PCB design guidelines of a particular communication bus.

USB have balanced signal characteristics so it is a good practice to match the impedance and consider the high speed routing practices.

Have a look at this:
https://www.ti.com/lit/an/slla414/slla414.pdf?ts=1612346420917&ref_url=https%253A%252F%252Fwww.google.co.in%252F