Can't get LTSpice to simulate a flip-flop

[special_K]

Hello again

I threw this flip-flop together in LTSpice using a CD4011 nand chip, and I can't get it to behave.

it doesn't remember it's state - the moment the input goes low, the output of U2 goes low too.

Using CircuitJS, it works correctly.

https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjCAMB0l3BWcMBMcUHYMGZIA4UA2ATmIxAUgpABZsKBTAWjDACgwEJttDwwUFAf0FVRFDlxA8+KFDSGC5CsdQRsA7tN4g0eRSKibtfAfq5L5RzhDA0FxWXn2OoutZNv3dNMc59UqkjqWjIgrij+rpDGYfJ++vFGWnYKeFSphjEp3srguQh82flpVISlRgDOIEzlIOkgdQ0ZIABmAIYANpUMbABKNU1UtQpgGEVuvtSBUNDqQA


The intended function is to control a relay - when U3 receives input from an overcurrent sensor, U4 should activate the (normally closed) relay and hold it open circuit. A momentary switch at U1 resets the state, making U4 low and closing the relay again.

[PGPG]

What do you expect at U3 input?

[special_K]

Nothing because there is no input to U3 yet.

It will eventually be the reset button. But no point in discussing reset, when set does not even work.

Tying U3 to gnd does not effect circuit. Neither does tying it to high logic level.

[Sensorcat]

It is not possible to debug this without the .asc file, because we don't see what is not drawn on the schematic. But looking at the model you have shown in your link, there is a big difference: There, you have gates which are abstractions from actual circuits, in LTspice, you have names of real components. This means that the model on falstad.com does work without power supply, but the CD4011B model you use in LTspice might need a supply. So the questions are:

• How is the gate model included in LTspice?
• How does the model file look like?

If you want an abstract model in LTspice, you can use the A-devices. They provide logic gates that are specified by paramaters, but do not resemble actual devices, and do not draw power.

[special_K]

The CD4011B comes from a zip file full of LTSpice crap I found on google at this site: http://www.bordodynov.ltwiki.org/

(first link, lib.zip, approx 20mb)

It does not have VDD or VCC pins in the symbol. It has a VDD value set in "SpiceLine", I know nothing else about it.

Actually simulating 4011 is important, not some ideal NAND.

[Sensorcat]

VDD wants to be set. Perhaps also VGND.

[special_K]

As far as I know, I've set VDD to 12 on all of the gates. There's no mention of VGND

[special_K]

Perhaps I should just give up on the LTSpice angle and instead breadboard it? A frustrating option because it means spending money and waiting for delivery.

[Jay_Diddy_B]

Hi,

Here is an example of how to make a two-input AND/NAND GATE using the AND gate found in the LTspice Digital Library.




The process

Start by selecting the AND gate from the LTspice Digital Library:




There are five inputs, two outputs and a ground:




Connect two of the inputs together, and connect three of the other input together. This reduces the number of inputs from 5 to 2.


It is necessary to specify the logic levels and the time constant. Details can found in the LTspice help:



CTRL-RIGHT_CLICK on the Gate symbol and edit the attributes:




Run the simulation.

Regards,

Jay_Diddy_B

 parameters in help.PNG (14.31 kB. 568x318 - viewed 14 times.)

[special_K]

I understand how to use the built-ins.

I don't want to though, because they are Ideal parts. If I want to use Idealized versions of parts then I use CircuitJS, which is a million times nicer than LTSpice's hostile UI.

The point of using LTSpice is to get a real simulation, with the foibles of the actual parts (or at least, a close approximation created by studying the real life parts). Remember that while logic gates work with digital information, the semiconductors themselves exist in the analogue world.

[PGPG]

Nothing because there is no input to U3 yet.

I have tried LTSpice only once many years ago. I practically don't know it.
Looking at your picture for example I don't know what V(n003) is.
Do the n003 is a standard net name everyone should know what it is.

I asked about U3 input because if it is read as 1 than U3 output should be 0 than forcing U4 output to be always 1 and in such case U4 can't work as half of flip-flop.

[Zero999]

Nothing because there is no input to U3 yet.

I have tried LTSpice only once many years ago. I practically don't know it.
Looking at your picture for example I don't know what V(n003) is.
Do the n003 is a standard net name everyone should know what it is.

I asked about U3 input because if it is read as 1 than U3 output should be 0 than forcing U4 output to be always 1 and in such case U4 can't work as half of flip-flop.

V denotes voltage, followed by the net name in brackets. No net name was defined, so LTSpice invented one: n003.

I understand how to use the built-ins.

I don't want to though, because they are Ideal parts. If I want to use Idealized versions of parts then I use CircuitJS, which is a million times nicer than LTSpice's hostile UI.

The point of using LTSpice is to get a real simulation, with the foibles of the actual parts (or at least, a close approximation created by studying the real life parts). Remember that while logic gates work with digital information, the semiconductors themselves exist in the analogue world.

The built-in gates are good enough for most applications. They can be made more realistic by filling out the fields shown by Jay_Diddy_B.

Failing that, post the models and symbols you've used, along with the .asc file, for those who don't want to download and install a huge library.

I've had a play.

If a pin on the gate is either connected directly to 0V or left unconnected, it is eliminated before the net list is generated and parsed to SPICE. If you want to remove V2, then R must be connected to 0V, via a pull-down resistor, to prevent it from being ignored. The unconnected pins can be hidden from the schematic, by unchecking mark unconnected pins, in options/control panel -> schematic/drafting options.

If the reference connection is left floating, it is automatically connected to 0V.

This circuit has a race condition, which stopped it from simulating. I managed to get it to work by slowing down A2, which ensures it always defaults to Q being low.

 Bistable NAND.asc (1.64 kB - downloaded 15 times.)

EDIT:
Here's the net list from the above .asc file

A1 0 S 0 S 0 N001 0 0 AND vhigh=12 Rout=200 Tau=2u
A2 0 N001 0 _Q 0 Q 0 0 AND vhigh=12 Rout=200 Tau=2.1u
A3 0 R 0 R 0 N002 0 0 AND vhigh=12 Rout=200 Tau=2u
A4 0 Q 0 N002 0 _Q 0 0 AND vhigh=12 Rout=200 Tau=2u
V1 S 0 PULSE(0 12 1m 1u 1u 1m 0 1)
V2 R 0 PULSE(0 12 9m 1u 1u 1m 0 1)
.tran 10m
.backanno
.end

It shows that all unconnected pins are connected to node 0 which is 0V. LT's SPICE engine is clearly ignoring all pins connected to node 0.

[xvr]

Actually simulating 4011 is important, not some ideal NAND.

Are you sure that the 4011 model obtained from the "zip file full of LTSpice crap" (your words) will be more accurate than the ideal model from LTSpice itself? Do you trust it?

[Zero999]

Actually simulating 4011 is important, not some ideal NAND.

Are you sure that the 4011 model obtained from the "zip file full of LTSpice crap" (your words) will be more accurate than the ideal model from LTSpice itself? Do you trust it?

I doubt the OP needs a highly accurate model for their application. It's just a basic flip-flop. I could understand if it were an analogue circuit such as an oscillator, amplifier, analogue switch etc. which is dependent on the gain, phase shift, input/output impedance of the gates, but it's not.

[PGPG]

I have tried LTSpice only once many years ago. I practically don't know it.
Looking at your picture for example I don't know what V(n003) is.
Do the n003 is a standard net name everyone should know what it is.

I asked about U3 input because if it is read as 1 than U3 output should be 0 than forcing U4 output to be always 1 and in such case U4 can't work as half of flip-flop.

V denotes voltage, followed by the net name in brackets. No net name was defined, so LTSpice invented one: n003.

The problem was - if you show signal make it clear at which circuit point these signal was taken.

[Zero999]

I have tried LTSpice only once many years ago. I practically don't know it.
Looking at your picture for example I don't know what V(n003) is.
Do the n003 is a standard net name everyone should know what it is.

I asked about U3 input because if it is read as 1 than U3 output should be 0 than forcing U4 output to be always 1 and in such case U4 can't work as half of flip-flop.

V denotes voltage, followed by the net name in brackets. No net name was defined, so LTSpice invented one: n003.

The problem was - if you show signal make it clear at which circuit point these signal was taken.

I agree. It was user error. It's good practice to name the nets you plot. I admit you'll probably find some of my old attachments, back when I didn't do so, but I was new to LTSpice and we all have to learn. I'm not having a go at anyone.

[special_K]

n003 was simply the output of U2, which I think is obvious from context

I doubt the OP needs a highly accurate model for their application. It's just a basic flip-flop. I could understand if it were an analogue circuit such as an oscillator, amplifier, analogue switch etc. which is dependent on the gain, phase shift, input/output impedance of the gates, but it's not.

A basic flip-flop has a random power on state. By simulating the exact IC I mean to use, then I can work on making it always start in one state. I have seen people do this by tacking on small caps to gate inputs.

This circuit has a race condition, which stopped it from simulating. I managed to get it to work by slowing down A2, which ensures it always defaults to Q being low.

The problem with doing it that way is you can't tell gates to be slower in real life...

[Zero999]

n003 was simply the output of U2, which I think is obvious from context

It's not obvious. Nets can be named with the Label Net command, or by pressing N and clicking on the relevant part of the circuit.

I doubt the OP needs a highly accurate model for their application. It's just a basic flip-flop. I could understand if it were an analogue circuit such as an oscillator, amplifier, analogue switch etc. which is dependent on the gain, phase shift, input/output impedance of the gates, but it's not.

A basic flip-flop has a random power on state. By simulating the exact IC I mean to use, then I can work on making it always start in one state. I have seen people do this by tacking on small caps to gate inputs.

Unfortunately that's impractical. To do that, you'll need to look at the IC you're using and measure the propagation delays/gains of each gate and develop a model specific to that IC. The problem is, as soon as you build another circuit, it will be different one, it'll give a different result. No two ICs will be alike, even if they have the same part number and the PCB layout will also make a difference.

[special_K]

n003 was simply the output of U2, which I think is obvious from context

It's not obvious. Nets can be named with the Label Net command, or by pressing N and clicking on the relevant part of the circuit.

I talked about the output of U2 going low, then showed a graph where a signal goes low.

It's not like I showed a graph with multiple signals. Just one. You do not have to be Sherlock Holmes.

[Zero999]

n003 was simply the output of U2, which I think is obvious from context

It's not obvious. Nets can be named with the Label Net command, or by pressing N and clicking on the relevant part of the circuit.

I talked about the output of U2 going low, then showed a graph where a signal goes low.

It's not like I showed a graph with multiple signals. Just one. You do not have to be Sherlock Holmes.

Why argue? Wouldn't it be better to simply accept it would have made it easier to understand and learn how to use net names? That's how I responded when someone raised the issue with me many years ago. You'll never learn anything with that defensive attitude.

Anyway, regarding the race condition. You can ensure the circuit always starts up in a certain state by adding an RC circuit. In this case the CD4xxxx logic series has a parasitic input capacitance of 7.5pF ( simulated by Cin on the schematic below) so adding a 1M resistor in series with one of the inputs will result in a time constant of 7.5µs.

Suppose the resistor is added to the input of A4 which is connected to A2's output. When the power is first applied, the input with the series resistor will always be at 0V for a short time, whilst the one connected to A3 will be high, which will make its output high. A2's output will then be low, because both of its inputs will be high.

The above approach should work in real life, but you might need a higher value resistor, or to add a real capacitor, if the power supply voltage doesn't increase sharply enough, at power on.