Cascading counters, something I do not get

[Moriambar]

Hello,
I was trying to experiment with some spare parts that were gifted to me and I stumbled into counters. Specifically, I have a load of 74AC163 (4 bit synchronous.

I was trying to cascade a bunch of them and count at different speeds (up to 10 or 20 MHz). Then I am puzzled.

The RCO pin, if I underrstand correctly is to be fed forward to the CLK of the next-in-line counter, in order to cascade them, BUT that pin transitions from low to high when the count is 0x0F, not when it is reset after a 0x0F (ie count of 0x10). So doesn't this produce the count 0x1F before the count 0x10?

I hope I made myself clear, I know I'm in the wrong, but I don't know how. Thanks

[Andy Watson]

The RCO pin, if I underrstand correctly is to be fed forward to the CLK of the next-in-line counter, in order to cascade them,

No. The RCO should connect to the ENT of the next counter. This will enable the clock of the next counter - whenever that clock occurs. Note, all counters should share the same clock.

[Moriambar]

The RCO pin, if I underrstand correctly is to be fed forward to the CLK of the next-in-line counter, in order to cascade them,

No. The RCO should connect to the ENT of the next counter. This will enable the clock of the next counter - whenever that clock occurs. Note, all counters should share the same clock.

ah! That's it, thanks

[Benta]

This could help:

https://www.eevblog.com/forum/oshw/how-to-programmable-divide-by-n-counters-using-standard-logic/

The only difference between 74AC161 and 74AC163 is the RESET signal, which is unimportant here.