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Chip making process
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TheUnnamedNewbie:

--- Quote from: ZeroResistance on October 18, 2018, 03:45:18 am ---So at the lowest level which among these can have the lowest feature size, diode, BJT, N Mosfet, P Mosfet. I mean in what order are the sizes of all these compos at the fabrication level?

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This depends on what you mean when you say 'lowest feature size'. I'd say a diode, since you pretty much form two diodes every time you make a MOS. In the CMOS technologies I have seen, the PMOS and NMOS device are the same size. The difference is that one of the two has to be placed in a well (usually the P-type device as we build on a p-substrate, so we first need to make an N-well). This makes the smallest possible isolated PMOS a bit bigger than the equivalent NMOS. But for analog design (and RF design even more so) we care mostly about the gate length, as that is one of the main factors in the electrical performance, and, in general, a shorter gate means a better transistor (but also a lower-voltage rated one - just a volt or less on the smallest of technologies).
Kjelt:

--- Quote from: ZeroResistance on October 18, 2018, 03:45:18 am ---So at the lowest level which among these can have the lowest feature size, diode, BJT, N Mosfet, P Mosfet. I mean in what order are the sizes of all these compos at the fabrication level?
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IIRC the conductivity of the P doping material (Boron i believe) is two to three times less than the N doping material (phosphor) which will result for the same current in a two to three time larger surface. This I guess is the reason the Power Fets these days are dominantly NFets ?  :-//
srce:

--- Quote from: ZeroResistance on October 18, 2018, 03:45:18 am ---So at the lowest level which among these can have the lowest feature size, diode, BJT, N Mosfet, P Mosfet. I mean in what order are the sizes of all these compos at the fabrication level?

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That depends on the process (and I guess what you mean by feature size). Here's the layout for the smallest pmos, nmos, diode and pnp in a 65nm CMOS process.

amyk:

--- Quote from: srce on October 18, 2018, 11:56:16 am ---and I guess what you mean by feature size
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This is important to call out because transistors on a IC do not exist as discrete units; they're effectively formed from the interaction between the different layers. You can see that even with something like this 4004 which uses a very old process: http://alumni.media.mit.edu/~mcnerney/2009-4004/4004-masks-composite.jpg
Jackson:

--- Quote from: Kjelt on October 18, 2018, 08:44:13 am ---
--- Quote from: ZeroResistance on October 18, 2018, 03:45:18 am ---So at the lowest level which among these can have the lowest feature size, diode, BJT, N Mosfet, P Mosfet. I mean in what order are the sizes of all these compos at the fabrication level?
--- End quote ---
IIRC the conductivity of the P doping material (Boron i believe) is two to three times less than the N doping material (phosphor) which will result for the same current in a two to three time larger surface. This I guess is the reason the Power Fets these days are dominantly NFets ?  :-//

--- End quote ---

Correct - for Silicon, hole mobility is 2-3x lower than it is for electron mobility, hence the rule of thumb to size up your PMOS transistor width to get equivalent current flow. If you're dealing with non-Silicon processes it will be different.
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