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Chip making process

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ZeroResistance:

--- Quote from: srce on October 18, 2018, 11:56:16 am ---
--- Quote from: ZeroResistance on October 18, 2018, 03:45:18 am ---So at the lowest level which among these can have the lowest feature size, diode, BJT, N Mosfet, P Mosfet. I mean in what order are the sizes of all these compos at the fabrication level?

--- End quote ---
That depends on the process (and I guess what you mean by feature size). Here's the layout for the smallest pmos, nmos, diode and pnp in a 65nm CMOS process.

--- End quote ---

This is simply amazing.
The PMOS and NMOS look similar sizes, the PMOS was supposed to be bigger right?
The diode seems to be bigger than the PMOS and NMOS, that was supposed to be the smallest.
And what is PNP that looks quite big?

Kjelt:

--- Quote from: ZeroResistance on October 18, 2018, 12:28:44 pm ---This is simply amazing.
The PMOS and NMOS look similar sizes, the PMOS was supposed to be bigger right?
--- End quote ---
Yes for the SAME current, in this case they are probably just "digital signal" fets for logical gates that do not need to source much current.

Kjelt:
Here is something to read, p14 and on

http://people.ee.duke.edu/~krish/teaching/Lectures/MOS.pdf

srce:

--- Quote from: ZeroResistance on October 18, 2018, 12:28:44 pm ---
--- Quote from: srce on October 18, 2018, 11:56:16 am ---
--- Quote from: ZeroResistance on October 18, 2018, 03:45:18 am ---So at the lowest level which among these can have the lowest feature size, diode, BJT, N Mosfet, P Mosfet. I mean in what order are the sizes of all these compos at the fabrication level?

--- End quote ---
That depends on the process (and I guess what you mean by feature size). Here's the layout for the smallest pmos, nmos, diode and pnp in a 65nm CMOS process.

--- End quote ---

This is simply amazing.
The PMOS and NMOS look similar sizes, the PMOS was supposed to be bigger right?

--- End quote ---
They're the same size. The minimum gate size for both is the same: L=60nm, W=120nm (but note the total area of the transistor is much bigger than this!) However, if you were making an inverter, due to the difference in carrier mobility, you might choose to make the PMOS bigger, to get similar rise/fall times, but you don't have to.


--- Quote from: ZeroResistance on October 18, 2018, 12:28:44 pm ---The diode seems to be bigger than the PMOS and NMOS, that was supposed to be the smallest.

--- End quote ---
It depends what you're actually measuring and how "good" a diode you want.


--- Quote from: ZeroResistance on October 18, 2018, 12:28:44 pm ---And what is PNP that looks quite big?

--- End quote ---
It's a vertical PNP BJT. It's a CMOS process, so the BJTs aren't great. If BJTs are what you're interested in, you need to look at BiCMOS or Bipolar process.


ZeroResistance:

--- Quote from: srce on October 18, 2018, 11:56:16 am ---That depends on the process (and I guess what you mean by feature size). Here's the layout for the smallest pmos, nmos, diode and pnp in a 65nm CMOS process.

--- End quote ---

BTW, what software is that?, are there any softwares where I can play around with I mean free ones. I have heard of Magic, ChipVault etc. will they do what you have shown in the image?

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