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| srce:
--- Quote from: ZeroResistance on October 19, 2018, 05:28:47 am --- --- Quote from: srce on October 18, 2018, 11:56:16 am ---That depends on the process (and I guess what you mean by feature size). Here's the layout for the smallest pmos, nmos, diode and pnp in a 65nm CMOS process. --- End quote --- BTW, what software is that?, are there any softwares where I can play around with I mean free ones. I have heard of Magic, ChipVault etc. will they do what you have shown in the image? --- End quote --- The major custom design package is Cadence Virtuoso. Also look at Synopsys Custom Compiler and Tanner AMS, which are less popular, but cheaper. What will really drive your selection will probably be what PDKs are available from the foundry you want to use, as they do not work with all tools. Magic is just a layout tool, I believe, and you need to draw everything by hand. The above have schematic driven layout using parameterizable cells, auto-routing and realtime DRC and simulation environments, etc. They're expensive, but if you're serious about IC design, then you'll need them. |
| ZeroResistance:
--- Quote from: srce on October 19, 2018, 08:29:58 am --- --- Quote from: ZeroResistance on October 19, 2018, 05:28:47 am --- --- Quote from: srce on October 18, 2018, 11:56:16 am ---That depends on the process (and I guess what you mean by feature size). Here's the layout for the smallest pmos, nmos, diode and pnp in a 65nm CMOS process. --- End quote --- BTW, what software is that?, are there any softwares where I can play around with I mean free ones. I have heard of Magic, ChipVault etc. will they do what you have shown in the image? --- End quote --- The major custom design package is Cadence Virtuoso. Also look at Synopsys Custom Compiler and Tanner AMS, which are less popular, but cheaper. What will really drive your selection will probably be what PDKs are available from the foundry you want to use, as they do not work with all tools. Magic is just a layout tool, I believe, and you need to draw everything by hand. The above have schematic driven layout using parameterizable cells, auto-routing and realtime DRC and simulation environments, etc. They're expensive, but if you're serious about IC design, then you'll need them. --- End quote --- ok! so did you place those components in Cadence Virtuoso? |
| srce:
This is Virtuoso - this time for a 28nm process - showing an NMOS, PMOS and VPNP as both schematic and layout. |
| ZeroResistance:
--- Quote from: srce on October 19, 2018, 11:16:17 am ---This is Virtuoso - this time for a 28nm process - showing an NMOS, PMOS and VPNP as both schematic and layout. --- End quote --- This is mind boggling! Many thanks again! The PNP is gigantic. The FETs in the symbols seem like JFET's so do they use JFET or MOSFET at the lowest level? I guess recently they have started with FinFet's.. |
| amyk:
People have successfully used free tools like MAGIC to make ICs: https://www.planetanalog.com/author.asp?section_id=526&doc_id=559519 There is analogy with PCB design, in that you can use a lot of different software but in the end the fab only needs the graphics for each layer, just like with PCB gerbers. |
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