Electronics > Beginners
Chip making process
srce:
--- Quote from: ZeroResistance on October 19, 2018, 11:48:24 am ---The PNP is gigantic.
--- End quote ---
I'm not sure that 1um is gigantic :P
--- Quote from: ZeroResistance on October 19, 2018, 11:48:24 am ---The FETs in the symbols seem like JFET's so do they use JFET or MOSFET at the lowest level?
--- End quote ---
You mean because they just have three terminals in the schematic? They are 4 terminal MOSFETs, but the symbol used has an implicit connection of the body to the source, so you don't have to wire it up manually each time. There's a different symbol you can use if you need to wire up the body separately.
ZeroResistance:
--- Quote from: srce on October 19, 2018, 12:39:35 pm ---You mean because they just have three terminals in the schematic? They are 4 terminal MOSFETs, but the symbol used has an implicit connection of the body to the source, so you don't have to wire it up manually each time. There's a different symbol you can use if you need to wire up the body separately.
--- End quote ---
It's my mistake I got the symbols wrong.
Coming back to the schematic you posted in Cadence Virtuoso.
There are some dimensions printed next to the component.
The nmos and pmos both show
w = 80n
l = 30n
m = 1
n = 1
I guess the w = width and l = length what are m and n?
So is a transistor sized 80n x 30n for a 28nm process?
srce:
--- Quote from: ZeroResistance on October 19, 2018, 12:52:59 pm ---Coming back to the schematic you posted in Cadence Virtuoso.
There are some dimensions printed next to the component.
The nmos and pmos both show
w = 80n
l = 30n
m = 1
n = 1
I guess the w = width and l = length what are m and n?
--- End quote ---
m = multiplier (E.g. if m=2, you get two separate transistors in parallel when you create the layout)
n = number of fingers (see picture for difference)
--- Quote from: ZeroResistance on October 19, 2018, 12:52:59 pm ---So is a transistor sized 80n x 30n for a 28nm process?
--- End quote ---
ish. W/L are the drawn dimensions of the channel (i.e. area of the gate (green bit) over the active (red)). If you include the extra area you need in order to connect to it, then it's bigger than that. This particular PDK actually has a scaling factor of 0.9 from what is in the design (So 30nm is scaled to 28nm (although it isn't really that simple)).
ZeroResistance:
--- Quote from: srce on October 19, 2018, 01:17:29 pm ---
--- Quote from: ZeroResistance on October 19, 2018, 12:52:59 pm ---Coming back to the schematic you posted in Cadence Virtuoso.
There are some dimensions printed next to the component.
The nmos and pmos both show
w = 80n
l = 30n
m = 1
n = 1
I guess the w = width and l = length what are m and n?
--- End quote ---
m = multiplier (E.g. if m=2, you get two separate transistors in parallel when you create the layout)
n = number of fingers (see picture for difference)
--- Quote from: ZeroResistance on October 19, 2018, 12:52:59 pm ---So is a transistor sized 80n x 30n for a 28nm process?
--- End quote ---
ish. W/L are the drawn dimensions of the channel (i.e. area of the gate (green bit) over the active (red)). If you include the extra area you need in order to connect to it, then it's bigger than that. This particular PDK actually has a scaling factor of 0.9 from what is in the design (So 30nm is scaled to 28nm (although it isn't really that simple)).
--- End quote ---
What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?
Same would have been the case with m=2 right?.
Is this done to increase the current being sourced / sinked?
Wimberleytech:
--- Quote ---What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?
Same would have been the case with m=2 right?.
Is this done to increase the current being sourced / sinked?
--- End quote ---
The purpose for building a transistor out of several transistors in parallel is for matching. If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor. This achieves better matching than simply building the 2x transistor 2x wider.
This is what I call the unit matching principle. It applies to MOS transistors, BJTs, resistors, capacitors, etc.
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