Electronics > Beginners
Chip making process
Wimberleytech:
Just a little cleanup...
For MOSFETs, Saturation is the state where Vds > Vgs - VT and Linear when Vds < Vgs - VT
When an MOS transistor is strongly on and Vds is near zero, it is operating in the Linear region, not Saturation region.
For CMOS logic gates, transistors spend precious little time in the Saturation region.
TheUnnamedNewbie:
--- Quote from: Wimberleytech on October 19, 2018, 02:21:20 pm ---
--- Quote ---What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?
Same would have been the case with m=2 right?.
Is this done to increase the current being sourced / sinked?
--- End quote ---
The purpose for building a transistor out of several transistors in parallel is for matching. If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor. This achieves better matching than simply building the 2x transistor 2x wider.
--- End quote ---
Another reason for this is to control the parasitic, and fold large transistors.
Foling large devices: Say you need a very wide transistor for something like a output driver stage, you might need a transistor that is 30 nm long and 15 um wide. That would be a very, very, very long thin line and just be annoying. So instead, you make it with (for example)100 parallel transistors that are 30 nm long, 150 nm wide.
Parasitics: Say you are making an RF amplifier. In this case you tend to tune out the gate capacitance with an inductor. Your gate poly/metal has resistance, which limits the effectiveness of the inductor and causes losses (and thus less system gain). A longer distance that the current has to travel though the gate results in more resistance. So you can try and make many connections across the length of the gate and drain, but that results in you getting more capacitance (because you are building two plates of a parallel plate capacitor). As a result, you get these kinds of tradeoffs (Source: P. Reynaert, 'Design of High Frequency Integrated Circuits', lecture slides):
EDIT: in case it is not clear what you are looking at: this is a '3D' view of the network to go from the top, ultra thick metal (neon green, top left of each image) to the gate/drain fingers of a transistor (teal-blue thing, bottom right). This is from a process that has, iirc, 9 metal layers + 1 UTM layer.
If you use less fingers, you need this taper to extend for a longer distance (gate-drain capacitance* + gate resistance go up). If you make shorter fingers, it will get too wide (gate-drain capacitance and gate resistance go down, gate-source/gate-substrate goes up).
*Note that the gate-drain capacitance isn't necessarily bad for the speed, but it is bad for stability as it provides a feedback path. In differential mode this can be tuned out (how is a topic for another time) but in common-mode it can't.
ZeroResistance:
--- Quote from: TheUnnamedNewbie on October 21, 2018, 06:15:49 am ---
--- Quote from: Wimberleytech on October 19, 2018, 02:21:20 pm ---
--- Quote ---What's the purpose of the fingers. What n=2 did what connect the 2 drains together and also the gates together and also the sources together. So in effect created 2 transistors in parallel? Correct?
Same would have been the case with m=2 right?.
Is this done to increase the current being sourced / sinked?
--- End quote ---
The purpose for building a transistor out of several transistors in parallel is for matching. If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor. This achieves better matching than simply building the 2x transistor 2x wider.
--- End quote ---
Another reason for this is to control the parasitic, and fold large transistors.
Foling large devices: Say you need a very wide transistor for something like a output driver stage, you might need a transistor that is 30 nm long and 15 um wide. That would be a very, very, very long thin line and just be annoying. So instead, you make it with (for example)100 parallel transistors that are 30 nm long, 150 nm wide.
Parasitics: Say you are making an RF amplifier. In this case you tend to tune out the gate capacitance with an inductor. Your gate poly/metal has resistance, which limits the effectiveness of the inductor and causes losses (and thus less system gain). A longer distance that the current has to travel though the gate results in more resistance. So you can try and make many connections across the length of the gate and drain, but that results in you getting more capacitance (because you are building two plates of a parallel plate capacitor). As a result, you get these kinds of tradeoffs (Source: P. Reynaert, 'Design of High Frequency Integrated Circuits', lecture slides):
EDIT: in case it is not clear what you are looking at: this is a '3D' view of the network to go from the top, ultra thick metal (neon green, top left of each image) to the gate/drain fingers of a transistor (teal-blue thing, bottom right). This is from a process that has, iirc, 9 metal layers + 1 UTM layer.
If you use less fingers, you need this taper to extend for a longer distance (gate-drain capacitance* + gate resistance go up). If you make shorter fingers, it will get too wide (gate-drain capacitance and gate resistance go down, gate-source/gate-substrate goes up).
*Note that the gate-drain capacitance isn't necessarily bad for the speed, but it is bad for stability as it provides a feedback path. In differential mode this can be tuned out (how is a topic for another time) but in common-mode it can't.
--- End quote ---
Thanks for sharing.
This is amazing and just goes to show the intricacies associated with chip design?
I guess all this came from your experience in chip design.
Is there a reference or book that would illustrate these practices, that one can read before diving into chip design?
ZeroResistance:
--- Quote from: TheUnnamedNewbie on October 21, 2018, 06:15:49 am ---The purpose for building a transistor out of several transistors in parallel is for matching. If you, for example, want to build a current mirror with a 2:1 ratio of currents, you build the 2x transistor out of two parallel versions of the 1x transistor. This achieves better matching than simply building the 2x transistor 2x wider.
--- End quote ---
So the width of a transistor is the length between Drain and Source or the Drain Source channel? Correct?
That means the gate would also be porportionately longer?
--- Quote ---EDIT: in case it is not clear what you are looking at: this is a '3D' view of the network to go from the top, ultra thick metal (neon green, top left of each image) to the gate/drain fingers of a transistor (teal-blue thing, bottom right). This is from a process that has, iirc, 9 metal layers + 1 UTM layer.
--- End quote ---
Yes its still not clear each layer seems to have finger shaped projections, so its not clear what is drain, gate or source.
I guess the solid block at the bottom is the substrate?
Richard Crowley:
--- Quote from: ZeroResistance on October 21, 2018, 08:33:56 am ---So the width of a transistor is the length between Drain and Source or the Drain Source channel? Correct?
--- End quote ---
Please refer to the image in response # 127.
If you look at the schematic diagram on the left, you will see that the notation says:
w=160n
l = 30n
That means that the gate LENGTH is 30n and the WIDTH is 160n
And if you look at the layout on the right side, the LENGTH is the distance between the Source and the Drain. And the WIDTH is the orthogonal measurement. You can eyeball that the WIDTH is about 5x the LENGTH distance.
The first layout shows a simple transistor. The second layout shows a transistor implemented in two sections ("n=2") where the total width is the same (160n), but it is broken up into two equal (80n) parts.
--- Quote --- its not clear what is drain, gate or source.
--- End quote ---
If you look closely at the layout (right side) of the image in #127, the Source is labeled with "/s/" and the Drain with "/d/" and the Gate with "/g/"
--- Quote ---I guess the solid block at the bottom is the substrate?
--- End quote ---
Yes.
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