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| TheUnnamedNewbie:
Transistors are formed in the front-end-of-line, which is where are the high temperature steps are done (for doping and forming the wells). Depending on the technology, you might have a metal or a poly-si gate. After that, you start counting metal layers (which would be the back-end-of-line, or BEOL) |
| srce:
--- Quote from: ZeroResistance on October 27, 2018, 06:35:18 pm --- --- Quote from: TheUnnamedNewbie on October 27, 2018, 06:20:34 pm ---In terms of metalization layers, I believe 8-12 is common now in chips, depending on what size and technology. For a long time they were limited to two, until chemical-mechanical polishing was perfected and allowed them to go for more metal layers. More metal layers don't really have negatives, except for the cost (more layers = more masks and more steps = more expensive). You don't have to use them, so they just open up more options. Ofcourse for micro/millimeter wave designers like me it does mean that we need more vias (and vias = resistance) to go from the thick top metals to the transistors. An advantage of more metal layers is that your capacitors get smaller (more capacitance/unit area since there are more metals to make plates with) --- End quote --- Would that mean that the transistors are formed on the bottom 3 - 4 layers and then above that would be additional metal layers. I mean out of the 12 layers you mentioned. --- End quote --- Nope. The standard terminology is that "layers" usually means "metal layers" and this is just the number of metal layers you have for routing. It doesn't have anything to do with transistors or number of masks, which will be a lot more. For example, take this http://www.europractice-ic.com/technologies_TSMC.php TSMC .18 process. Number of metal layers can be from 3 to 6, so you'll often hear this be called a 6 metal layer process. However, the number of masks is given as between 26 and 31. You need one mask for each metal layer + a mask for the vias inbetween the metal layers. Then most of the other masks are basically to make the transistors. |
| Kjelt:
In laymens terms you have a few to tens of nm structures on the bottom but you need to : - connect the G,S,D to power and other logical elements - connect the end pads at the end to the ics bonding pads that will be some tens to hundreds of microns large. So in the metal layers you do the routing but also in steps scaling up from nm to um structures. That is also why only for the lowest layers you need the most precise litho machines while for the higher layers you can also use the somewhat less precise litho machines if the overlay is matching. |
| TheUnnamedNewbie:
There are these two classic images by, if I'm not mistaken, intel and IBM: Intel, 11 metal layers. Clearly shows how metals are getting thicker. Green is a low-k dielectric, used to reduce capacitance (due to the high \$\epsilon_{R}\$ of silicon, the parasitic capacitance would be very high if SiO would be used all the way to the top layers): IBM. In this one you can see the fins (this is a prototype 10 nm fin-fet process) of the transistors at the bottom): Also notice how, esp on the lower layers, the metals have a very repeatable pattern. A lot of these thin metals might not actually be connected, but they are added because it gives a more repeatable and constant profile, and gives better results in the CMP process. Here is another nice image to show you just how big a scale difference there is between these layers. The red tiny things at the bottom would be the poly of the gates (under the blue layers). Big pink bottom is the substrate. (this image is the connection to a differential pair for a oscillator). Tha transistors would be under neath all of this mess, under the dark blue lines (where the tiny red bits pop out). Source: Wouter Steyaert, THz electronics in nanometer CMOS. PDF: https://core.ac.uk/download/pdf/84932070.pdf |
| ZeroResistance:
--- Quote from: Kjelt on October 28, 2018, 10:18:36 am ---In laymens terms you have a few to tens of nm structures on the bottom but you need to : - connect the G,S,D to power and other logical elements - connect the end pads at the end to the ics bonding pads that will be some tens to hundreds of microns large. So in the metal layers you do the routing but also in steps scaling up from nm to um structures. That is also why only for the lowest layers you need the most precise litho machines while for the higher layers you can also use the somewhat less precise litho machines if the overlay is matching. --- End quote --- I got the G, S, D part. but what are end pads? and why do you scale up from nm to um as you move top the layers? |
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