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Chip making process

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TheUnnamedNewbie:

--- Quote from: ZeroResistance on October 15, 2018, 05:48:46 am ---
--- Quote from: srce on October 13, 2018, 07:35:20 pm ---
For prototyping, you want to use a multi-project-wafer (MPW). This will typically give you 40 to 50 die. Costs are a few thousand to hundred thousand, depending on the technology and die size. See here for actual pricing:

 http://www.europractice-ic.com/docs/180719_MPW2018-miniasic-v7.0.pdf


--- End quote ---
1. Had a look at that document, so they give prices for 1mm2 of silicon. So how much does fit on 1mm2 of silicon?
the Last I heard it is 100k gates for 0.18u. And each subsequent process node with double the density so for eg. 0.13u will be 200k gates.

--- End quote ---

The thing is that not all transistors are the same size - something which is even more so the case for analog design. Just because you can make a tiny 200nmx30nm transistor, doesn't mean that you want to. Matching, gain, noise, all are reasons why you want to play around with sizes.


--- Quote from: ZeroResistance on October 15, 2018, 05:48:46 am ---2. So how many transistors make a gate ?

--- End quote ---

Depends on the gate. Ranges from two (inventor) to a few dozen.


--- Quote from: ZeroResistance on October 15, 2018, 05:48:46 am ---3. What about analog how many op-amps will fit in that area, or adc? It would be good to know if there is any document that shows transistor count per analog block? Like adc, dac, op-amp etc.

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You can't do this because it all depends on specs. For obvious reasons, making a simple opamp that has little gain, poor offset, and works to 200 kHz will be a lot easier to design than a high-performance 2 GHz GBW amplifier. You can always look up a few standard opamp/OTA configurations to get a ball-park idea but even then you can't really say much.

The fact that digital logic is getting a lot smaller, and as a result calibration is being applied /everywhere/ (calibrate out offsets etc) this only gets more complex.

1 mm^2 of chip area can give you a lot of stuff though. Often people get limited by IO area - if you bond, you can only fit so much rows of bond pads on your chip.

ZeroResistance:
How does power electronics fit into all this? Is that a totally different process?
I mean makig a power mosfet or a power half bridge.
What kinds' of processes are used for those?

TheUnnamedNewbie:

--- Quote from: ZeroResistance on October 15, 2018, 06:41:29 am ---How does power electronics fit into all this? Is that a totally different process?
I mean makig a power mosfet or a power half bridge.
What kinds' of processes are used for those?

--- End quote ---

There are special processes used often for power electronics or automotive. These tend to have much higher breakdown voltages. Though there are some things you can do with modern CMOS, it's hard. (and I've only ever seen it done for applications where it has to be a single-chip solution because of volume (length-times-width-times-height volume, not amount of chips) and weight reasons. What is also possible is a multiple-dies-in-package solution, where you will combine a CMOS die with a power-fet die inside a single package.

mikeselectricstuff:
If you look at the thousands of very cheap Chinese chips for simple analogue functions that sell for a few cents, there must be some fairly cheap route for this type of design.
You probably need to speak Mandarin to access it though.

srce:

--- Quote from: mikeselectricstuff on October 15, 2018, 08:11:11 am ---If you look at the thousands of very cheap Chinese chips for simple analogue functions that sell for a few cents, there must be some fairly cheap route for this type of design.
You probably need to speak Mandarin to access it though.

--- End quote ---
Older processes analog processes are much cheaper. You could knock out a design for under $100k, including tools. But even if for more modern processes, it's still possible to make very cheap parts, providing you are selling millions of them. Because although the NRE costs are high, the actual cost per mm of silicon is low  (E.g. a couple of $k per wafer, depending on the process).

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