Electronics > Beginners
Chip making process
Richard Crowley:
--- Quote from: ZeroResistance on October 28, 2018, 01:29:10 pm ---I got the G, S, D part.
but what are end pads? and why do you scale up from nm to um as you move top the layers?
--- End quote ---
Simply so that they are large enough to actually make a connection into the Real World.
Contact pads that seem as large as an aircraft carrier (when viewed from the perspective where you can "see" individual transistors) are barely visible in the Real World unless viewing through a microscope.
We once printed out the die layout of a CPU chip (386 IIRC) so that it was 30 feet across. The bond pads were something around 4 inches 100mm square and the plot filled one wing of the cafeteria. But even at that resolution, the individual transistors weren't really visible. They were only 2-3 pixels in size.
ZeroResistance:
--- Quote from: TheUnnamedNewbie on October 28, 2018, 11:06:27 am ---There are these two classic images by, if I'm not mistaken, intel and IBM:
Intel, 11 metal layers. Clearly shows how metals are getting thicker. Green is a low-k dielectric, used to reduce capacitance (due to the high \$\epsilon_{R}\$ of silicon, the parasitic capacitance would be very high if SiO would be used all the way to the top layers): ...
--- End quote ---
This is mind bogglingly amazing!!
How on earth do you get such great images?!
Interesting thing that you talk about the repeatable pattern. And there also seems to be a pattern on the upper half of the thick substrate layer (the bottommost one).
What patterns are those?
Are the substrate and the 2 layers above it, the transistors?
With regards to the bottom most image what kind of program generates such kind of design, is it a CAD program or a specialized IC design software?
Also, when do you use polysilicon and when do you use metal, I guess both thes are used for interconnects right?
TheUnnamedNewbie:
--- Quote from: ZeroResistance on October 28, 2018, 01:56:09 pm ---
--- Quote from: TheUnnamedNewbie on October 28, 2018, 11:06:27 am ---There are these two classic images by, if I'm not mistaken, intel and IBM:
Intel, 11 metal layers. Clearly shows how metals are getting thicker. Green is a low-k dielectric, used to reduce capacitance (due to the high \$\epsilon_{R}\$ of silicon, the parasitic capacitance would be very high if SiO would be used all the way to the top layers): ...
--- End quote ---
This is mind bogglingly amazing!!
How on earth do you get such great images?!
Interesting thing that you talk about the repeatable pattern. And there also seems to be a pattern on the upper half of the thick substrate layer (the bottommost one).
What patterns are those?
Are the substrate and the 2 layers above it, the transistors?
--- End quote ---
The transistors are completely in the bottom layers. For a planar process (bulk CMOS, not FINFET), the transistors look like this (source):
This is all made before the first metal layer is deposited. There are some small differences between processes (metalgate, self-aligned transistors) but that would take us too far. Everything is built out of the original silicon, with exception of the two bumps. After this is made (everything up to this point is called front-end-of-line) we start with metals (back-end-of-line).
Fin-Fets, which is what you see in the second picture, involves growing fins. It's these fins I think you are talking about.
No metals are involved in making the actual transistors, they are only used after the transistors are made, to connect them to each other (exception would be metal-gate, but again, details that are not important now).
--- Quote from: ZeroResistance on October 28, 2018, 01:56:09 pm ---
With regards to the bottom most image what kind of program generates such kind of design, is it a CAD program or a specialized IC design software?
--- End quote ---
When we design such a thing we use a combination of tools: Cadence Layout (G)XL (to do the actual drawing of materials), Keysight EEsof ADS/momentum (first, fast simulations of simpler structures), Ansys HFSS (detailed high-performance analysis of EM stuff), Mentor Calibre (Layout-vs-schematic and parasitic-extraction, though the latter isn't that usefull anymore to us, since we simulate with EM simulators). It is all hand-drawn, there isn't some auto-generator for it.
To get the nice 3D plot: I believe the university of Twente has a nice 3D GDSII viewer, which is often used for that. Mind you, apart from making nice images for publications and such we don't tend to use it much.
ZeroResistance:
--- Quote from: TheUnnamedNewbie on October 28, 2018, 02:21:06 pm ---Fin-Fets, which is what you see in the second picture, involves growing fins. It's these fins I think you are talking about.
--- End quote ---
Is the second picture in the link you provided because I don't see it in the post?
ZeroResistance:
--- Quote from: TheUnnamedNewbie on October 28, 2018, 02:21:06 pm ---
The transistors are completely in the bottom layers. For a planar process (bulk CMOS, not FINFET), the transistors look like this (source):
This is all made before the first metal layer is deposited. There are some small differences between processes (metalgate, self-aligned transistors) but that would take us too far. Everything is built out of the original silicon, with exception of the two bumps. After this is made (everything up to this point is called front-end-of-line) we start with metals (back-end-of-line).
--- End quote ---
1. For NMOS why make a p-Si well when a P-Si already exists?
2. What is punch stop?
3. What is STI?
4. The silicide layers are used as conductors? But then why the gate has n+poly also where as the drain and source has only silicide and no n+ poly?
I guess I'll do some searches on the internet and see what answer each of those questions return?
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