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Chip making process

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Wimberleytech:

--- Quote from: ZeroResistance on October 28, 2018, 03:19:11 pm ---
--- Quote from: TheUnnamedNewbie on October 28, 2018, 02:21:06 pm ---
The transistors are completely in the bottom layers. For a planar process (bulk CMOS, not FINFET), the transistors look like this (source):



This is all made before the first metal layer is deposited. There are some small differences between processes (metalgate, self-aligned transistors) but that would take us too far. Everything is built out of the original silicon, with exception of the two bumps. After this is made (everything up to this point is called front-end-of-line) we start with metals (back-end-of-line).



1. For NMOS why make a p-Si well when a P-Si already exists?

--- End quote ---
The main reason is that the doping profile of each well can be individually tailored.  Also provides isolation benefits

--- Quote ---2. What is punch stop?

--- End quote ---
Not sure

--- Quote ---3. What is STI?

--- End quote ---
Shallow Trench Isolation 
This technique replaces  the old LOCOS technique

--- Quote ---4. The silicide layers are used as conductors? But then why the gate has n+poly also where as the drain and source has only silicide and no n+ poly?

--- End quote ---
Yes, silicide is a refractory metal--a conductor.
Polysilicon is the preferred material to make defect-free gates.  Metal is terrible as the gate-oxide interface
There is no need for poly at the source and drains.
--- End quote ---

ZeroResistance:
Just a few questions that come to my mind while contemplating on the topic

1. Why is the silicon wafer when its being manufactured from a liquid kind of state not 100% pure silicon?. Why is it doped to become an N type or a P Type substrate? I mean some dopants are added to the mix when the wafer is being manufactured?

2. Why is an epitaxial coating done over the silicon wafer before any other processes are done?

3. Is there a comprehensive list of steps for silicon chip  fabrication?

TIA

Wimberleytech:

--- Quote from: ZeroResistance on January 28, 2019, 04:39:22 pm ---Just a few questions that come to my mind while contemplating on the topic

1. Why is the silicon wafer when its being manufactured from a liquid kind of state not 100% pure silicon?. Why is it doped to become an N type or a P Type substrate? I mean some dopants are added to the mix when the wafer is being manufactured?

--- End quote ---

This is a deep and involved topic with lots of history. 
Lets work backwords from the transistor structure.
An N-channel transistor needs N+ source and drain (the "+" indicates heavy doping of donor atoms) diffused into silicon doped with acceptor atoms so that the underlying material is doped P type.  In order to achieve desired transistor performance, that material is very lightly doped...we call it P- where the "minus" means lightly doped.  In the above, Phosphorous is typically used as a donor dopant, and Boron is used as an acceptor dopant.

If all you wanted to build were N-channel transistors, you could manufacture a silicon wafer that has a P- doping.  In fact, early MOS technology was either totally N-channel, or totally P-channel.  Of course, for a totally P-channel circuit, the wafer would have to be manufactured with N- doping.

Wafers come from silicon ingots, or boules, that are manufactured using the Czochralski method.  Molten silicon is gradually extracted starting with a crystalline seed.  For doping requirements, the molten silicon can be doped with donors or acceptors to achieve the desired doping.

Nobody uses NMOS, or PMOS any more.  CMOS instead!!  So, how do you put a p-channel transistor in a wafer that is already doped P- ?? 

Well, you have to create regions on the wafer that are lightly doped N-.  These regions are called "wells."  So, for CMOS, you may start with a lightly doped P- wafer as the basic substrate, then create well that is doped N- (either by ion implantation, or diffusion, or combination of both).  Withing the n-well, you can put p-channel transistors.  In the regions outside of the well, you can put the n-channel transtors.  Now you have CMOS!! 

That is pretty much it, except for about a million other details.



--- Quote ---2. Why is an epitaxial coating done over the silicon wafer before any other processes are done?

--- End quote ---
Epi layers can be created with more precise and tuned properties than can be achieved with the C-growth method.  The underlying substrate can be high conductivity enabling better performance under certain condition.

--- Quote ---3. Is there a comprehensive list of steps for silicon chip  fabrication?

--- End quote ---

Yes.  Have you googled for this?
Also, the processing steps of changed over the years-- metal-gate, silicon-gate, oxide-isolated, shallow-tranch isolation, on and on...

Go here: https://aicdesign.org/wp-content/uploads/2018/08/lecture02-131209.pdf

Richard Crowley:

--- Quote from: ZeroResistance on January 28, 2019, 04:39:22 pm ---3. Is there a comprehensive list of steps for silicon chip  fabrication?
--- End quote ---

https://en.wikipedia.org/wiki/Semiconductor_device_fabrication#List_of_steps

That is as good as you are going to get if you are asking for a list of generic types of processes.

If you are asking about the exact steps for a particular device or fab process, that is typically a closely-held secret.

ZeroResistance:

--- Quote from: Wimberleytech on January 28, 2019, 05:44:30 pm ---
An N-channel transistor needs N+ source and drain (the "+" indicates heavy doping of donor atoms) diffused into silicon doped with acceptor atoms so that the underlying material is doped P type.  In order to achieve desired transistor performance, that material is very lightly doped...we call it P- where the "minus" means lightly doped.  In the above, Phosphorous is typically used as a donor dopant, and Boron is used as an acceptor dopant.


--- End quote ---
The "diffused" term that you use here what does that do? I heard that ion implantation is used to for adding impurities (doping) to the silicon wafer. What does diffusion do?

Secondly you refer to the wafer being lightly doped either N- or P-.
Is that it because from what I had read so far is that the subtrate is heavily doped P+ or N+ and on top of this there is a lightly doped epitaxial layer grows P- or N-.

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