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| brucehoult:
--- Quote from: Wimberleytech on January 29, 2019, 09:19:15 pm ---At my last company (which I started), I dont think we ever did an ALR--maybe one. That was out of about a dozen base platforms. Tools are just so good, and with a solid methodology, you can get it mostly right (tweak with metal fix) every time. Now, doing RF or extreme precision...perhaps another story. --- End quote --- I agree with this. Maybe some analogish problem, but there's not much excuse for bad digital design now, especially if you don't overly complicate the design with seldom-used features. At SiFive we use "agile hardware design". You can see Dave Paterson talking about it here You can test fundamentals in tools such as Verilator, but pretty quickly you want to get into an FPGA where you can run at 50 MHz or 100 MHz and boot up Linux, build and test any software you want, even run SPEC in a week. You should be able to exercise the design enough that when it gets moved into an ASIC there are no show-stoppers. |
| Wimberleytech:
--- Quote from: brucehoult on January 30, 2019, 12:03:34 am --- --- Quote from: Wimberleytech on January 29, 2019, 09:19:15 pm ---At my last company (which I started), I dont think we ever did an ALR--maybe one. That was out of about a dozen base platforms. Tools are just so good, and with a solid methodology, you can get it mostly right (tweak with metal fix) every time. Now, doing RF or extreme precision...perhaps another story. --- End quote --- I agree with this. Maybe some analogish problem, but there's not much excuse for bad digital design now, especially if you don't overly complicate the design with seldom-used features. At SiFive we use "agile hardware design". You can see Dave Paterson talking about it here You can test fundamentals in tools such as Verilator, but pretty quickly you want to get into an FPGA where you can run at 50 MHz or 100 MHz and boot up Linux, build and test any software you want, even run SPEC in a week. You should be able to exercise the design enough that when it gets moved into an ASIC there are no show-stoppers. --- End quote --- I had my team synthesize all of the digital to FPGA back in 1999. We were certain of the logic. When pushing speed, a little different story. You cannot do a lot with analog spares, but there was one occasion where a designer was expecting a low-side bias current but the verilog model (which drove the hookup) had high-side bias. Obviously did not work. Solution? I had designed an analog spare block that allowed for an easy turn-around mirror. Saved an all-layer rev. plus it was quick...and on VC money, time is everything. |
| ZeroResistance:
--- Quote from: Wimberleytech on January 30, 2019, 12:31:37 am ---I had my team synthesize all of the digital to FPGA back in 1999. We were certain of the logic. When pushing speed, a little different story. You cannot do a lot with analog spares, but there was one occasion where a designer was expecting a low-side bias current but the verilog model (which drove the hookup) had high-side bias. Obviously did not work. Solution? I had designed an analog spare block that allowed for an easy turn-around mirror. Saved an all-layer rev. plus it was quick...and on VC money, time is everything. --- End quote --- 1. This sounds interesting. How does one make a one size fits all spare block. Because in the end anything could go wrong or have a bug. 2. Was this bug discovered after the masks were made? 3. Did you have to redo some masks after correcting this? |
| Wimberleytech:
--- Quote ---1. This sounds interesting. How does one make a one size fits all spare block. Because in the end anything could go wrong or have a bug. --- End quote --- You don't. Just do the best you can. Build transistor arrays, P, and N. Make them long channel, cascoding ability. Scale them so that you can mirror up or down. I cannot recall what else I used. --- Quote ---2. Was this bug discovered after the masks were made? --- End quote --- Discovered when power was applied to first prototype units! Because I had run copious extra "spare metal" it was an easy FIB to fix and verify. --- Quote ---3. Did you have to redo some masks after correcting this? --- End quote --- Yes. Metal mask only. Went to production using the spare analog cells. |
| coppice:
--- Quote from: Wimberleytech on January 30, 2019, 02:42:44 pm ---it was an easy FIB to fix and verify. --- End quote --- Easy and FIB is a combination of words I don't often see. :) |
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