Electronics > Beginners
Chip making process
srce:
--- Quote from: ZeroResistance on October 15, 2018, 05:53:17 am ---
--- Quote from: amyk on October 15, 2018, 04:04:22 am ---I've heard that the Chinese foundries will let you get your own chips made at a tiny fraction of the cost of the traditional approaches, if you happen to know the right people....
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Any idea which chinese foundries?
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SMIC. But, lots of have partner programs (E.g. https://www.globalfoundries.com/design-services/fdxcelerator-partner-program) that potentially could be persuaded if you have some really interesting IP. They're not going to do it for fun, though.
srce:
--- Quote from: ZeroResistance on October 15, 2018, 05:48:46 am ---1. Had a look at that document, so they give prices for 1mm2 of silicon. So how much does fit on 1mm2 of silicon?
the Last I heard it is 100k gates for 0.18u. And each subsequent process node with double the density so for eg. 0.13u will be 200k gates.
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Look on these pages: http://www.europractice-ic.com/technologies_TSMC.php?tech_id=90nm and look through the different nodes for Gate density.
--- Quote from: ZeroResistance on October 15, 2018, 05:48:46 am ---2. So how many transistors make a gate ?
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gate count is usually lowest drive strength, 2-input NAND equivalent rather than transistor counts (So 1 gate = 4 transistors).
--- Quote from: ZeroResistance on October 15, 2018, 05:48:46 am ---3. What about analog how many op-amps will fit in that area, or adc? It would be good to know if there is any document that shows transistor count per analog block? Like adc, dac, op-amp etc.
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It's not just about transistors though. In analog blocks, much of the area will be for capacitors and resistors - these don't scale much between processes. (E.g. capacitance is roughly proportional to area, so it doesn't matter what process you are using (to a first order)).
srce:
--- Quote from: brucehoult on October 15, 2018, 03:57:36 am ---[Disclaimer: I liked what they're doing so much I joined the company]
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How many licensees do you have now?
srce:
--- Quote from: ZeroResistance on October 15, 2018, 06:41:29 am ---How does power electronics fit into all this? Is that a totally different process?
I mean makig a power mosfet or a power half bridge.
What kinds' of processes are used for those?
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What voltages? You'll probably need something specialised: https://www.xfab.com/markets/applications/high-voltage/
brucehoult:
--- Quote from: srce on October 15, 2018, 09:01:07 am ---
--- Quote from: brucehoult on October 15, 2018, 03:57:36 am ---[Disclaimer: I liked what they're doing so much I joined the company]
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How many licensees do you have now?
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I don't know exactly, and I wouldn't be allowed to say anyway :-) Certainly a lot more than have publicly announced products, which is something that just started to happen in August. The pipeline from deal to announced/shipping product can be quite long. And definitely there are licencees who will never make any public announcement about it.
Some who have announced to date:
FADU: enterprise SSD controller in 7nm with multiple E51s (64 bit, no MMU) https://www.prnewswire.com/news-releases/fadu-launches-industry-leading-ssd-solutions-powered-by-sifive-risc-v-core-ip-300693176.html
Mobiveil: E51 and U54 complex (similar to the HiFive Unleashed board) embedded in an FPGA as a configurable SSD controller https://www.prnewswire.com/news-releases/mobiveil-inc-and-sifive-inc-partner-to-develop-risc-v-based-configurable-ssd-platform-for-data-center-and-enterprise-storage-applications-300693280.html
eSilicon: E2-series core (32 bit, 2-stage pipeline), in SerDes applications. This one is in 7 nm FinFET https://www.prnewswire.com/news-releases/esilicon-licenses-industry-leading-sifive-e2-core-ip-for-next-generation-serdes-ip-300692833.html
Huami: E31 based SoC for IoT/fitness applications https://abopen.com/news/huami-announces-risc-v-based-fitness-wearables-smartwatch/
Of course Western Digital is well known to be a customer and investor in SiFive.
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