Chip making process

[brucehoult]

So what is the terminology is a reticle = a mask? 

Yes it is.

I believe in FAB usage mask and reticule are actually alternatives.

A mask is the same size as the silicon wafer and the entire wafer is exposed in one operation. A reticule is effectively a small (e.g. 25mm x 25mm) but very precise mask and each part of the wafer is exposed in turn, using a very accurate stepper mechanism.

[ZeroResistance]

So what is the terminology is a reticle = a mask? 

Yes it is.

I believe in FAB usage mask and reticule are actually alternatives.

A mask is the same size as the silicon wafer and the entire wafer is exposed in one operation. A reticule is effectively a small (e.g. 25mm x 25mm) but very precise mask and each part of the wafer is exposed in turn, using a very accurate stepper mechanism.

So lets say I send my design to the mask maker and he sends me back a 1mm2 size mask or reticule and for each of the layers.
Or does the mask maker make a grid of the whole design based on what the foundry silicon wafer size is, and and then gives me that for all the layers And then this is submitted to the foundry right? and then they expose the whole wafer at one go and you get he desired number of chips from that wafer.
This would be the process wouldn't it?
In what case would the foundry want to selectively expose a reticule? Because that seems to be a very slow process?

[Kjelt]

I believe in FAB usage mask and reticule are actually alternatives.
A mask is the same size as the silicon wafer and the entire wafer is exposed in one operation. A reticule is effectively a small (e.g. 25mm x 25mm) but very precise mask and each part of the wafer is exposed in turn, using a very accurate stepper mechanism. 

I never heard of that. Perhaps in the far past it was done that way with 2" wafers or so but modern stepper scanners contain a reticle holding a single processstep of a single or more dies(chips). This depends on the size of the die. And the wafer is exposed in steps (stepper) or in a scan (scanner) where the reticule and the wafer move in opposite directions (see wiki below).
The whole wafer is so exposed in a couple of scans which totally takes less than 10 seconds.
These machines nowadays do 250 wafers/hour.
https://en.wikipedia.org/wiki/Stepper

BTW the reason is simple you can not focus an entire wafer upto the required nm resolution, your lens would be 1meter diameter and more expensive than the entire fab. The reticule is 4x bigger than the final die so if any dust particle is on the reticle it will not influence the final product.

[Richard Crowley]

I remember in the late 1970s, 4-inch (100mm) wafers were still being exposed with whole-die wafer methods using equipment from Perkin-Elmer.  Their optical division developed the Keyhole-9 satellite spy cameras and were later responsible for the Hubble optical system.  When feature sizes started getting smaller, it was getting difficult to expose a whole wafer because minute vibration would blur the image. I remember at one time personnel were deployed as train-spotters to warn of approaching rail traffic so that they could suspend imaging while the train passed.  Giant timbers were wedged between the ground-floor slab and the floor of the fab to reduce the vibration.

As @Kjelt mentioned, current practice is to use 4x reticles to step and repeat exposure across 300mm wafers.  Laser interferometery is used to ensure accurate positioning for each exposure.  And it is good enough that it has operated perfectly during an earthquake. A far cry from the days of wedged timbers and trainspotting.

ED: "whole-wafer", not "whole-die"!

[coppice]

I remember in the late 1970s, 4-inch (100mm) wafers were still being exposed with whole-die methods using equipment from Perkin-Elmer.  Their optical division developed the Keyhole-9 satellite spy cameras and were later responsible for the Hubble optical system.  When feature sizes started getting smaller, it was getting difficult to expose a whole wafer because minute vibration would blur the image. I remember at one time personnel were deployed as train-spotters to warn of approaching rail traffic so that they could suspend imaging while the train passed.  Giant timbers were wedged between the ground-floor slab and the floor of the fab to reduce the vibration.

As @Kjelt mentioned, current practice is to use 4x reticles to step and repeat exposure across 300mm wafers.  Laser interferometery is used to ensure accurate positioning for each exposure.  And it is good enough that it has operated perfectly during an earthquake. A far cry from the days of wedged timbers and trainspotting.

The exposure is about the same size now. The active area of the reticule is of the order of 100mm x 100mm.

[srce]

So lets say I send my design to the mask maker and he sends me back a 1mm2 size mask or reticule and for each of the layers.
Or does the mask maker make a grid of the whole design based on what the foundry silicon wafer size is, and and then gives me that for all the layers And then this is submitted to the foundry right? and then they expose the whole wafer at one go and you get he desired number of chips from that wafer.
This would be the process wouldn't it?

For an MPW - you don't have anything to do with masks or reticles. You wont even get to see them. You'll create a GDS file containing the design - send that off - and you'll get dies back in the post. You don't really need to understand anything about the manufacturing process (aside from the purpose of each layer in the GDS file of course )

Generally, IC designers just talk about masks, and don't really care about the distinction. The only time you care, is if your die size is limited by the reticle size, but you shouldn't be anywhere near that.

[srce]

We need to remember that those prices are for untested / unpackaged chips and how to handle unpackaged chips would be another topic of discussion, hope someone puts in more info regarding this.

You will get the dies from Europractice in a little tray like this:



You can just forward that to the packaging house, without even opening it. But if you do, because you'll obviously want a look , don't worry, too much, they'll probably survive even if you fiddle with them with tweezers (you can get proper tools). Just don't forget the ESD structures on your IO pads!

Europractice can do packaging - I personally use: http://www.icproto.com/ in the USA. You need to send them a bonding diagram showing how the bond pads should be bonded to the package pins:



And give them some other details like diameter of the bond wires, what metal to use and of course what package you want, and a logo / marking. It will take them about a week (with postage) to do it. A couple of dies may be damaged in the setup process.

You may want to split it in to two lots for packaging, in case you make a mistake in your bonding diagram or they get lost in the post!

You'll need to design the test procedure yourself!

[Wimberleytech]

I remember in the late 1970s, 4-inch (100mm) wafers were still being exposed with whole-die methods using equipment from Perkin-Elmer. 

4" single mask (per layer) were common into the 80's.

--I think you meant "whole-wafer" btw.

[Wimberleytech]

In the old days, a reticle was made first from the database.  Using the reticle, a mask was made.  In these photos, you see a retical, the mask that was made from the reticle, and the wafer that was made from the mask (obviously, only one layer is represented).

Somewhere around here, I have a reticle used for a modern step-and-repeat system, but I cannot find it 

Ahaa...here is the reticle

The die is stepped on this redical (5x5) and the 8" wafer is made by stepping this reticle

[ZeroResistance]

You will get the dies from Europractice in a little tray like this:

Whats the problem in soldering the die directly to a pcb? are the bond pads too small that they can't be soldered directly to the board, similar to a LGA package? And then pour epoxy on it similar to a COB package. Like many chinese items have.

[ZeroResistance]

Just tried X-raying a 10F200 and 10F322 - unfortunately the die wasn't visible through the leadframe, but estimating from where the bond pads were, I'd guess 2-3mm^2

What kind of equipment did you use to xray that chip?

[wraper]

You will get the dies from Europractice in a little tray like this:

Whats the problem in soldering the die directly to a pcb? are the bond pads too small that they can't be soldered directly to the board, similar to a LGA package? And then pour epoxy on it similar to a COB package. Like many chinese items have.

Not only they are too small, why do you think they are solderable in the first place? You can make die it solderable to the PCB but it's a special process.

[ZeroResistance]

Ok, so lets say Microchip wants to release a new 10F chip and its a 2mm^2 area per chip.
The would obviously have to get it made in a foundry.
What kind of costs would be they be looking at.
For the masks, and for getting it made at the foundry. Would Microchip need to place an order for 1 million pcs of the chip?
How do these things work out, will the foundry charge by area of silicon, that would me 2 million mm^2 of area.
Packaging would be a seperate expense right?

[mikeselectricstuff]

Just tried X-raying a 10F200 and 10F322 - unfortunately the die wasn't visible through the leadframe, but estimating from where the bond pads were, I'd guess 2-3mm^2

What kind of equipment did you use to xray that chip?

Faxitron MX20 - unfortunately only does 35kv so barely makes it through the leadframe

[coppice]

Ok, so lets say Microchip wants to release a new 10F chip and its a 2mm^2 area per chip.
The would obviously have to get it made in a foundry.
What kind of costs would be they be looking at.
For the masks, and for getting it made at the foundry. Would Microchip need to place an order for 1 million pcs of the chip?
How do these things work out, will the foundry charge by area of silicon, that would me 2 million mm^2 of area.
Packaging would be a seperate expense right?

Someone like Microchip would not contract for a complete device. They might use an in house fab or they might use a foundry, but the production of the wafers will be one commercial step. They will contract for a specified number of wafers, based on the expected yield of good dies meeting their needs. Next they will send the wafers to an assembly and test place, as a second commercial step, separate from the wafer production. Again this may be an in house operation, or the work may be given to an assembly and test contractor. These two operations - assembly and test - usually go together. You need to test a wafer, to locate the good dies. Then you package the good dies. Finally you need to test again, to make sure the packaging went OK. Having the packaging step between two test steps usually leads to them being bundled into an activity at a single site. People like TSMC and UMC are famous as wafer foundries, but there is also a group of less widely known large contract assembly and test companies. The program for the tester will usually be provided and maintained by the chip designers - they are the ones who know what the chip should do, and what needs testing.

Many of the largest silicon companies have no fabs, assembly or test facilities of their own. They do, however, usually have extensive labs of their own. These can get really expensive for a startup, but trying to work without them can be a huge drag on productivity. Things like FIB (focused ion beam) machines don't come cheap, but can be a huge boon when trying to diagnose and work around silicon bugs.

[Wimberleytech]

Ok, so lets say Microchip wants to release a new 10F chip and its a 2mm^2 area per chip.
The would obviously have to get it made in a foundry.
What kind of costs would be they be looking at.
For the masks, and for getting it made at the foundry. Would Microchip need to place an order for 1 million pcs of the chip?
How do these things work out, will the foundry charge by area of silicon, that would me 2 million mm^2 of area.
Packaging would be a seperate expense right?

Here is ballpark based on what a 0.35um flash silicided poly, 4 layers of metal, with cap poly and poly resistor options
Mask costs not included here.

[ZeroResistance]

You need to test a wafer, to locate the good dies. Then you package the good dies. Finally you need to test again, to make sure the packaging went OK.

If a wafer has 100 dies on it what would be the typically percentage of good dies?

[ZeroResistance]

Ok, so lets say Microchip wants to release a new 10F chip and its a 2mm^2 area per chip.
The would obviously have to get it made in a foundry.
What kind of costs would be they be looking at.
For the masks, and for getting it made at the foundry. Would Microchip need to place an order for 1 million pcs of the chip?
How do these things work out, will the foundry charge by area of silicon, that would me 2 million mm^2 of area.
Packaging would be a seperate expense right?

Here is ballpark based on what a 0.35um flash silicided poly, 4 layers of metal, with cap poly and poly resistor options
Mask costs not included here.

This is pretty amazing, did you rattle that off in a few minutes.
Just a bit out of depth with the terminology what does MLO mean? What's is probe yield?
How many wafers do I have to order from the foundry to get these sort of rates?

[coppice]

You need to test a wafer, to locate the good dies. Then you package the good dies. Finally you need to test again, to make sure the packaging went OK.

If a wafer has 100 dies on it what would be the typically percentage of good dies?

Yield depends a LOT on the complexity of the dies and what your pass/fail requirements are. If you have a hard transistor failure you have a dead die, but die may fail because their analogue parts are out of spec, or something won't run at full speed. Your test program can also affect yield, which is something non-obvious to outsiders, but you eventually find can have a real impact on profitability.

For an example, look at the Wimberleytech's information. Hist costs look high, so they may be old. His probe yield and final test yield are reasonable for the geometry and size of die he has, assuming its a tolerant design. An intolerant design (i.e. one where everything has to be just right to pass the production tests) may give much worse yields. If your wafer has only 100 dies they will be huge dies, and the yield will be a lot worse.

[srce]

For the masks, and for getting it made at the foundry. Would Microchip need to place an order for 1 million pcs of the chip?
How do these things work out, will the foundry charge by area of silicon, that would me 2 million mm^2 of area.

They charge a one off fee for the masks, then per wafer.

Packaging would be a seperate expense right?

Yes

[srce]

You need to test a wafer, to locate the good dies. Then you package the good dies. Finally you need to test again, to make sure the packaging went OK.

If a wafer has 100 dies on it what would be the typically percentage of good dies?

Yield depends on process maturity and die size (as well as some other factors) If a wafer only has 100 dies - that suggests they're monster dies and thus the yield would be relatively low. For a more realistic die size on a mature process, you should be looking at 98%. You'll also have a packaging yield as well.

[ZeroResistance]

Just tried X-raying a 10F200 and 10F322 - unfortunately the die wasn't visible through the leadframe, but estimating from where the bond pads were, I'd guess 2-3mm^2

What kind of equipment did you use to xray that chip?

Faxitron MX20 - unfortunately only does 35kv so barely makes it through the leadframe

Doesn't the leadframe surround the die, I mean the die is in the center and the leadframe is surrounding it but only on the XY plane? And there is just the plastic packaging on the top.
So just needed to understand how that interfers with the Xray?

[Richard Crowley]

What's is probe yield?

Dice are tested on the wafer before the wafer is sawed apart into dice.
Probe-cards are used to make connection with all the bond-pads so that the die can be tested.
They used to actual put a drop of ink on the bad dice, but now the good/bad information is stored in a database for that wafer.
That way they don't waste time/materials packaging bad dice.

https://www.mjc.co.jp/en/technology/column/probe_card.html

[ZeroResistance]

For the masks, and for getting it made at the foundry. Would Microchip need to place an order for 1 million pcs of the chip?
How do these things work out, will the foundry charge by area of silicon, that would me 2 million mm^2 of area.

They charge a one off fee for the masks, then per wafer.

Packaging would be a seperate expense right?

Yes

Do foundries have a minimum wafer quantity. I mean wemberlytech showed cost of a wafer as USD 1600. So do the foundries expect you to order something like 100 wafers.
And if each wafer has 15000 dies on it. Do the foundries also charge you per die on that wafer.
I guess it should have been area based, if a wafer is 200mm in dia that comes to 31400mm^2. So Do they charge on area of silicon?

[Wimberleytech]

This is pretty amazing, did you rattle that off in a few minutes.
Just a bit out of depth with the terminology what does MLO mean? What's is probe yield?
How many wafers do I have to order from the foundry to get these sort of rates?

This came from my files.  In my former life, I was founder and CTO of a fabless semiconductor company.
MLO = Materials Labor Overhead
Probe yield:  prior to packaging, each die on the wafer is probed and tested.  Only some of these die will pass the probe test...thus the probe yield.
After packaging, the die are tested again.  Less then 100% of the packaged units will yield--package yield.
To work with a foundry, you will have to commit to many thousands of wafers in production.
For this example, I do not recall which package was being used (maybe 32 pin pqfp).