Electronics > Beginners
Chip making process
ZeroResistance:
I hope the learned and experienced folks over here would shed some light on the chip making process, I mean more so with if we want to get chips made what is the whole pipeline associated with it?
I have a few questions and hope the learned folks address it
1. If I have a schematic that consists a op-amp amplifier and say a mosfet driver would this finally be flattened to transistors at the lowest level.
Will the same be applicable for digital circuits?
2. Do I have to select a process node like 22nm etc.. or does the foundry decide that?
3. If I have tested by circuit using a specific op-amp from TI and mosfet driver from Fairchild, how do I ensure that he same spec gets transferred to the final flattened transistors?
4. What tools are required for creating and sending the designs to mask maker and foundry?
5. What are the costs and MOQ involved in the whole process?
6. I have heard of companies like MOSIS / Europractice who work with low volumes. Do these companies handle the whole process from mask making and dealing with the foundry on their own. Does any of you have any experience in dealing with these companies?
Thanks in Advance!
TheUnnamedNewbie:
--- Quote from: ZeroResistance on October 13, 2018, 09:21:13 am ---I hope the learned and experienced folks over here would shed some light on the chip making process, I mean more so with if we want to get chips made what is the whole pipeline associated with it?
I have a few questions and hope the learned folks address it
1. If I have a schematic that consists a op-amp amplifier and say a mosfet driver would this finally be flattened to transistors at the lowest level.
Will the same be applicable for digital circuits?
--- End quote ---
This is not how ASIC design works. You don't use a TI op-amp, you design your own (or use IP blocks, but that is a different story, and last time I checked, only really a thing for digital). Usually you have a top-down-to-bottom-up design: the team starts with a high level architecture and then starts defining blocks which then have to meet a certain spec. You then use that spec to choose a circuit topology and size your transistors. Then you go back and verify it meets the specs - if you have a lot of excess room you can see if the higher level specs can be tweaked (eg, if you have a power budget of 10 mW, and you planned your output driver to use 2 mW, and your modulator to use 1 mW, but it turns out your output driver spec can be met with just 1 mW, you can allow yourself some more headroom on the modulator).
For digital circuits, the standard way is to use HDL to describe the circuit. Sometimes you manually size bits, but that is not that common (I think - I'm not a digital designer).
--- Quote from: ZeroResistance on October 13, 2018, 09:21:13 am ---2. Do I have to select a process node like 22nm etc.. or does the foundry decide that?
--- End quote ---
You decide this. There are a lot of factors that go into selecting the technology. Smaller nodes give higher cost per area, but higher density. Analog performance increases, though this has been less and less the case in the last decade. Transitors also behave differently on different technologies - if I take a design from a 0.18 um node, I can't just copy it to 28nm.
Within a technology, you often even select what flavour. What special bells 'n whistles do you want? IO transistors with higher breakdown? How many different VT's do you want? Do you want UTM (ultra-thick metal)? MIM capacitors? How many metal layers? TSVs?
--- Quote from: ZeroResistance on October 13, 2018, 09:21:13 am ---3. If I have tested by circuit using a specific op-amp from TI and mosfet driver from Fairchild, how do I ensure that he same spec gets transferred to the final flattened transistors?
--- End quote ---
As stated in 1. this is not how ASIC design works, and hence this is not a problem that exists.
--- Quote from: ZeroResistance on October 13, 2018, 09:21:13 am ---4. What tools are required for creating and sending the designs to mask maker and foundry?
--- End quote ---
Depends on what you are doing. The industry standard tool for analog ASIC design is Cadence Virtuoso. Costs a lot of money. Like, a lot.
The main tools you tend to use in analog is a spice engine and a layout tool. You first do a design in spice, and then would implement a layout (similar to PCB layout). Depending on the nature of the design, you do PEX (parasitic extraction) to verify you still meet your spec.
If you are into digital, I don't really know what the standard tools are. Usually some logic synthesis tool, and a place-and-route tool (most digital stuff is - mostly - auto-routed).
If you go to RF (my field, so I am a bit more familiar with this), things get more expensive. In addition to all the stuff analog designers use, we use more complicated spice engines (that can do stuff like harmonic balance, periodic steady-state, etc...). The reason for these is because we have very high frequencies and very low frequencies at the same time - the start-up of a VCO can take a lot of time (when compared to the period of the oscillation). The fact that it oscillates at perhaps 20 GHz means that you need a very, very small time step, and as a result you need long simulation times. Special tools can use fancy tricks to get around this.
We also use various types of EM simulators. ADS-Momentum is very common for transformer/inductor design. HFSS is common for on-chip antenna or larger structures.
--- Quote from: ZeroResistance on October 13, 2018, 09:21:13 am ---5. What are the costs and MOQ involved in the whole process?
--- End quote ---
Depends.
--- Quote from: ZeroResistance on October 13, 2018, 09:21:13 am ---6. I have heard of companies like MOSIS / Europractice who work with low volumes. Do these companies handle the whole process from mask making and dealing with the foundry on their own. Does any of you have any experience in dealing with these companies?
Thanks in Advance!
--- End quote ---
My job involves working with Europractice. They do a lot for you. However, I'm not sure how much I can say as a lot of foundry stuff is under NDA. In general you buy area through europractice and then put whatever you want on there (provided it is DRC clean).
srce:
--- Quote from: ZeroResistance on October 13, 2018, 09:21:13 am ---4. What tools are required for creating and sending the designs to mask maker and foundry?
--- End quote ---
Usually a combination of tools from Synopsys, Cadence and Mentor. Typical set might be:
For digital: RTL / gate-level simulation (ModelSim), Synthesis (Design Compiler), Place and Route (IC Compiler), ATPG (TetraMax), STA (PrimeTime), Rail Analysis (PrimeRail), Equivalence checking (Formality)
For analog: Schematic & Layout (Virtuoso), Simulation (Spectre)
For both: DRC / LVS / RCX (Calibre)
--- Quote from: ZeroResistance on October 13, 2018, 09:21:13 am ---5. What are the costs and MOQ involved in the whole process?
--- End quote ---
The tools mentioned above cost tens of thousands of dollars each!
For prototyping, you want to use a multi-project-wafer (MPW). This will typically give you 40 to 50 die. Costs are a few thousand to hundred thousand, depending on the technology and die size. See here for actual pricing:
http://www.europractice-ic.com/docs/180719_MPW2018-miniasic-v7.0.pdf
When you go to production, you're looking at millions of dollars for the latest technologies, but old stuff can be a couple of hundred thousand. MOQ is how many die fit on a wafer.
--- Quote from: ZeroResistance on October 13, 2018, 09:21:13 am ---6. I have heard of companies like MOSIS / Europractice who work with low volumes. Do these companies handle the whole process from mask making and dealing with the foundry on their own.
--- End quote ---
They don't make the masks. They just combine the design you send them, with those from other companies, for the MPW, and handle some logistics & customer support etc, so you don't have to deal with the foundry. All you need to do is send Europractice your GDS file (which is an image of each layer of your IC design) and a some cash :D
srce:
--- Quote from: TheUnnamedNewbie on October 13, 2018, 12:03:13 pm ---(or use IP blocks, but that is a different story, and last time I checked, only really a thing for digital).
--- End quote ---
Yeah, you can get analog IP. But it isn't as portable between different processes as digital, so it's often not available for the exact process you want. This means there's often an extra cost for porting and extra risk given the differences.
srce:
If you have a real project and some cash, I'd suggest you talk to an ASIC design services company, who will have all the tools and specialise in making ICs for companies who don't have the experience.
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