Circuit design with logic gates - in practice

[tggzzz]

200MHz+ 'scope will help diagnose signal integrity problems, especially with a 5k:50R divider, ie 5k resistor on the end of some 50 ohm coax, with 50 ohm load at the scope-end - such a low-impedance probe is more faithful to the actual voltages, especially if the probe ground lead is short and direct (low inductance).

Yes. Such low impedance resistive divider Z0 probes have a higher tip impedance than the traditional 10Mohm "high" impedance probes. Fundamental principle is that they have lower tip capacitance, so load the circuit less and self-resonate at higher frequencies.

[tychob]

The "X with analogue bandwidth of Y" is, of course a question based on an inaccurate premise. The transition time is what matters. I suggest you read the references I gave earlier in this thread, search for Bogotins rules of thumb, and read manufacturers application notes.

Analogue bandwidth is an important value. Because thats how an oscilloscope front end is specified. And a big part of the question here is: If I have X oscilloscope, and Y logic gate, where Y gate does not specify a minimum rise time, only a minimum time between edges to have an effect, how can I be confident that the oscilloscope will see any noise that would trigger the gate?

That 0.35 magic number after all is a characterization of the oscilloscope front end.

I wouldn't bother with coax; for critical lines and slow/medium speed logic twisted pair is equivalent.

It is usually easiest to base a prototype on a solid ground plane, and keep wires close to the plane. Failing that, approximate a ground plane by having a grid of wires that approximate a ground plane.

Once you understand the theory, you will be able to understand what you can (and can't) get away with in practice. In the absence of that, use short wires over a ground plane.

For examples of old and new techniques, see https://entertaininghacks.wordpress.com/2020/07/22/prototyping-circuits-easy-cheap-fast-reliable-techniques/

Why are twisted pairs sufficient, why a ground plane? In the absence of actual understanding, I'm faced with a bunch of 'cargo cult' rules. I'd like to see somewhere I can read more on how to achieve reliable clock distribution on manhatten, because I can't seem to find anything that isn't in one of the extremes of 'just use a breadboard', or 'keep the clock to a dedicated PCB devboard'. Or even just some more resources on things like how to attach adapters so they are grounded appropriately. Theres plenty of resources on how to use strip board or breadboards without a ground plane.

200MHz+ 'scope will help diagnose signal integrity problems, especially with a 5k:50R divider, ie 5k resistor on the end of some 50 ohm coax, with 50 ohm load at the scope-end - such a low-impedance probe is more faithful to the actual voltages, especially if the probe ground lead is short and direct (low inductance).

And where does one find an affordable 200MHz scope? An older DSO?

[TimFox]

What textbooks on logic system design and construction have you consulted?

[tychob]

What textbooks on logic system design and construction have you consulted?

Which textbooks would you recommend that include practical, mechanical construction advice? Because so far I've been limited to app notes and online sources.

[TimFox]

My textbooks are not up-to-date on high-speed digital construction.
You might start with the usual suspect, "Art of Electronics" by Horowitz and Hill.
Look at the current edition at your local library, and see how much of your concerns are covered, then look at the references to cover other details.

[tggzzz]

The "X with analogue bandwidth of Y" is, of course a question based on an inaccurate premise. The transition time is what matters. I suggest you read the references I gave earlier in this thread, search for Bogotins rules of thumb, and read manufacturers application notes.

Analogue bandwidth is an important value. Because thats how an oscilloscope front end is specified. And a big part of the question here is: If I have X oscilloscope, and Y logic gate, where Y gate does not specify a minimum rise time, only a minimum time between edges to have an effect, how can I be confident that the oscilloscope will see any noise that would trigger the gate?

That 0.35 magic number after all is a characterization of the oscilloscope front end.

Sigh.

My latest scope puts its principal specification on the front panel: 200ps risetime. The corresponding 1.7GHz is buried in the manual, since it is unimportant.

I wouldn't bother with coax; for critical lines and slow/medium speed logic twisted pair is equivalent.

It is usually easiest to base a prototype on a solid ground plane, and keep wires close to the plane. Failing that, approximate a ground plane by having a grid of wires that approximate a ground plane.

Once you understand the theory, you will be able to understand what you can (and can't) get away with in practice. In the absence of that, use short wires over a ground plane.

For examples of old and new techniques, see https://entertaininghacks.wordpress.com/2020/07/22/prototyping-circuits-easy-cheap-fast-reliable-techniques/

Why are twisted pairs sufficient, why a ground plane? In the absence of actual understanding, I'm faced with a bunch of 'cargo cult' rules. I'd like to see somewhere I can read more on how to achieve reliable clock distribution on manhatten, because I can't seem to find anything that isn't in one of the extremes of 'just use a breadboard', or 'keep the clock to a dedicated PCB devboard'. Or even just some more resources on things like how to attach adapters so they are grounded appropriately. Theres plenty of resources on how to use strip board or breadboards without a ground plane.

Read the resources mentioned. Then ask a question based on what you have learned.

200MHz+ 'scope will help diagnose signal integrity problems, especially with a 5k:50R divider, ie 5k resistor on the end of some 50 ohm coax, with 50 ohm load at the scope-end - such a low-impedance probe is more faithful to the actual voltages, especially if the probe ground lead is short and direct (low inductance).

And where does one find an affordable 200MHz scope? An older DSO?

On fleabay or at a hamfest. My latest one cost £25. I wouldn't recommend that path to a beginner, except where they are sure the scope is working correctly.

Older DSOs suck rocks and should be avoided like the plague. Exception: capturing single-shot events. Until the last decade they had many characteristics that fooled beginners and annoyed professionals. They were, however, mostly better than analogue storage scopes.

[tggzzz]

What textbooks on logic system design and construction have you consulted?

Which textbooks would you recommend that include practical, mechanical construction advice? Because so far I've been limited to app notes and online sources.

Which ones have you read, and what have you learned from them?

It sounds like you want to avoid understanding theory. If that is the case then you will be limited to doing "monkey-see monkey-do" work.

Having said that, some of these might be relevant: https://entertaininghacks.wordpress.com/library-2/bookshelf/

[tychob]

What textbooks on logic system design and construction have you consulted?

Which textbooks would you recommend that include practical, mechanical construction advice? Because so far I've been limited to app notes and online sources.

Which ones have you read, and what have you learned from them?

It sounds like you want to avoid understanding theory. If that is the case then you will be limited to doing "monkey-see monkey-do" work.

Having said that, some of these might be relevant: https://entertaininghacks.wordpress.com/library-2/bookshelf/

Its not that I want to avoid it, so much as my experience so far is that every time I make one step forward in learning theory, I learn two new things I still need to know before I understand. My current projection is a decade to actually understand enough theory. So I'm looking for a path that does allow making things before finishing that. Because I don't think trying to learn the equivelent of an EE degree on my own with no support and limited time is something I can manage. And at the moment, all I see are cargo cult and embracing unreliability.

[tggzzz]

...my experience so far is that every time I make one step forward in learning theory, I learn two new things I still need to know before I understand. My current projection is a decade to actually understand enough theory.

You are simultaneously too optimistic and too pessimistic.

The "learn one thing discover two things you don't know" is real, and everybody experiences it. It is neverending. That's a principal joy of any intellectual profession.

Who the hell wants to be doing the same thing for the rest of their life?! And in addition anybody who thinks it will be possible is destined to be thrown on the scrap heap in a couple of decades.

The concept of "The Red Susan's Race" is as valid now as it was in 1865. Deal with it!

[tggzzz]

So long as you aren't running a system anywhere near f_max and you follow synchronous design practises, then ringing induced glitches aren't going to cause you actual problems, (because sampling time), and for overshoot, the protection diodes are specified to be able to take up to 20mA of that. So unless you are driving hard and fast, none of these are actually necessarily problems.

So long as power is well decoupled, and the clocks are clean enough to remain monotonic, then synchronous digital logic is remarkably robust to bad signal integrity on the data paths, if the clock sampling frequency is sufficiently below the design speed f_max to allow time for ringing glitches to propagate out.

It would have been better for a beginner if you explicitly addressed the point you explicitly excluded: signal integrity on the clock line.

That is a classic problem area, especially if poor construction allows non-monotonic clock transitions. I've seen many beginner's constructions have problems like that.

Signal integrity on data lines is, of course, far less demanding. That's a key advantage of clocked designs.

To focus on this then, what construction practices do prevent double clocking? One thing I have thought about in theory but not tried is distributing the clock to dedicated flipflop modules by coax.

Double-clocking is potentially an issue, but I suspect not for the reasons you are thinking of. I've never seen a case of double clocking because a transmission line wasn't uses.

I'd be far more concerned that double-clocking might occur because of ground bounce in either the tx or rx, or - where the ground plane is insufficient - in some nearby but apparently unrelated buffer/line driver. There's a more probable cause of flip flop misbehaviour which might be incorrectly assigned to double clocking.

Most beginners concentrate on a flip-flop's setup time, since that directly affects the circuits "headline advertised" max speed. But if inadequate setup time is a possibility, it can easily be tested by slightly reducing the clock frequency and seeing if the problem disappears.

But there's another requirement for correct flip-flop behaviour: the hold time. The hold time is (in practice) noticeably shorter than the setup time. Importantly, in any given circuit reducing the clock frequency will not improve the hold time. To emphasise that, if you have a marginal failure with a 10MHz clock, you will still have the same marginal failure with a 1Hz clock.

That ties in with why, when considering signal integrity, thinking in terms of a digital system's clock frequency is simply wrong.

Now consider a clock line with poor signal integrity. If the edge is non-monotonic, it will be slower and that will erode the hold time.

Ground bounce can have the same consequences.

[rstofer]

Have you Googled 'high speed digital logic physical layout'?  There might be some useful information.

[tychob]

There's lots of information. Much of it contradictory. Much of it directly contradicts what has already been said in this thread. Much of it has way too much assumed theory knowledge to be usable by someone who struggles with the implications of transmission line theory, let alone a beginner who doesn't know what a transmission line is yet. Useful trustworthy and understandable information? Much harder to find.

[tggzzz]

There's lots of information. Much of it contradictory. Much of it directly contradicts what has already been said in this thread. Much of it has way too much assumed theory knowledge to be usable by someone who struggles with the implications of transmission line theory, let alone a beginner who doesn't know what a transmission line is yet. Useful trustworthy and understandable information? Much harder to find.

The fundamentals aren't contradictory. OTOH the application of the fundamentals to one situation might be completely different to another situation. That might appear contradictory.

When I was young information was hard to acquire. Hobbyist magazines (with very variable quality), books from a bookshop (few, most with superficial indotmation and many gaps), books from the library (read a catalogue, wait a month). Consequently the key skill was the read carefully multiple times to extract everything.

Now data is trivial to acquire, and the key skill is to rapidly determine what should be ignored.
That will only get worse with websites created by LLMs; I've already noticed that happening and getting high up in a gurgle search.
That will only get worse since anybody can proclaim themselves an expert and disseminate their misunderstandings. See Yooootooob for examples.

Welcome to the modern world.


I suspect you are watching too many yoootooob vids, and odd blogs braindumps, and forums where random people give half-baked explanations.

So, do the hard work to read textbooks to understand the theory; there is no substitute. Read application notes to understand application of theory.

[dmills]

For a book that is a good mix of theory and 'rules of thumb' that can be applied without needing to understand Heaviside (He was robbed by Maxwell!), take a look at "High speed signal propagation - advanced black magic', it hits a nice Balance IMHO.

Regards, Dan.

[tggzzz]

For a book that is a good mix of theory and 'rules of thumb' that can be applied without needing to understand Heaviside (He was robbed by Maxwell!), take a look at "High speed signal propagation - advanced black magic', it hits a nice Balance IMHO.

Regards, Dan.

I've pointed him towards a set of books I have found useful over the years, one of which is clearly directly relevant to his current situation. I haven't seen any indication that he has looked at the list let alone a book.

He has been refreshingly open about his current situation here: https://www.eevblog.com/forum/beginners/circuit-design-with-logic-gates-in-practice/msg5165619/#msg5165619

[c64]

For learning digital logic "old school" style (without FPGA or CPLD) I would use SPLD, for example ATF16v8 or ATF22v10
Just buy bunch or them in DIP package and always install in sockets. Easy to reuse in your next project, simple language, easy PCB routing.

Can buy them new or second hand. Latest version of TL866 can program them, or you can make programmer yourself (google afterburner)

[MrAl]

Hi all

I'm quite new to circuit designing using gates IC (for example a NAND gate), I usually design with an MCU but I'm trying to implement logic without MCUs, using gates.

I could not find any "proper" examples of a schematic using those ICs (any gate IC).

My questions are:

• Should you use current limiting resistors on the gate's inputs?
• Should you make sure the gate's inputs are pulled low or high while the circuit starts up (using f.x. a 10k pull-down res)?
• Can you simply connect directly the output of one gate to the input of another?
• I assume decent decoupling for each gate IC is necessary on the power pins, just like with an MCU?
• What about considerations like rise-time and fall-time, should one add a low value (say 100pF) cap on the output of a gate?

And as I understood gates inputs are basically the "gate pin" of a Mosfet, and if I was using a Mosfet I would definitely use a current limiting resistor (to avoid having huge currents while the gate is charging) and a pulldown. Though in the few schematics I have seen - as I said it's hard to find any  - people seem to simply connect inputs and outputs without caring about these things.

Any thoughts?
Thank you

PS: this is what I'm trying to design: https://www.eevblog.com/forum/beginners/sending-a-digital-signal-with-an-rc-circuit/
(but these questions are much more general about gates and has nothing to do as such with the project, so I thought it deserved a new topic)

Hello,

Most logic gate technology is made to be connected to another input without an issue.
For CMOS, if you were to use a resistor from the output of one gate to the input of another gate that would cause an extra undesirable propagation delay.
There are some other rules you should obey such as power supply bypassing and stuff like that though.

For the design implementation, you could design the circuit ad-hoc and then use Boolean Algebra to reduce the circuit to a minimum configuration of gates.

[Saimoun]

Amazing guys, thank you all for the long list of info and the debate in this topic
I have my answers, but feel free to keep the debate going without me 

[Terry Bites]

Here are few pdf books you can get for free. TI, Nexperia, Onsemi etc have stacks of logic design notes.

https://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwiKru_HxsuCAxXEWUEAHfqMClEQFnoECBIQAQ&url=https%3A%2F%2Fmrcet.com%2Fdownloads%2Fdigital_notes%2FIT%2FDIGITAL%2520LOGIC%2520DESIGN%2520(R17A0461).pdf&usg=AOvVaw3uP434gzTyaTU1cNQpfb65&opi=89978449

https://www.google.co.uk/url?sa=i&url=http%3A%2F%2Fbitsavers.informatik.uni-stuttgart.de%2Fcomponents%2Fti%2F_dataBooks%2F1988_TI_Advanced_CMOS_Logic_Designers_Handbook.pdf&psig=AOvVaw12WLeLkiEQ5_fL6pkWDSEz&ust=1700327717528000&source=images&cd=vfe&opi=89978449&ved=0CBQQjhxqFwoTCMjL8cPEy4IDFQAAAAAdAAAAABAD

https://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwiSyKWRxsuCAxXgXUEAHVL-PGAQFnoECBQQAQ&url=https%3A%2F%2Farchive.org%2Fdownload%2FDigitalLogicAndComputerDesignByM.MorrisMano2ndEdition%2FDigital%2520Logic%2520And%2520Computer%2520Design%2520By%2520M.%2520Morris%2520Mano%2520%25282nd%2520Edition%2529.pdf&usg=AOvVaw0bEHRcdIwKEfYTi30lJmMB&opi=89978449

[fourfathom]

For CMOS, if you were to use a resistor from the output of one gate to the input of another gate that would cause an extra undesirable propagation delay.

This is mostly true, but some CMOS is fast enough and some traces are long enough that putting a series resistor at the driver output (and perhaps an R/C termination at the end of the trace) is called for.  Not necessary in most cases, and I've designed plenty of fast designs with direct and unterminated connections, but we used to need to do this when using ECL logic (yes, I know that ECL is not CMOS), and some modern CMOS is just as fast as ECL.

[MrAl]

For CMOS, if you were to use a resistor from the output of one gate to the input of another gate that would cause an extra undesirable propagation delay.

This is mostly true, but some CMOS is fast enough and some traces are long enough that putting a series resistor at the driver output (and perhaps an R/C termination at the end of the trace) is called for.  Not necessary in most cases, and I've designed plenty of fast designs with direct and unterminated connections, but we used to need to do this when using ECL logic (yes, I know that ECL is not CMOS), and some modern CMOS is just as fast as ECL.

Hi,

Yes that's a good point.  If the output has to drive any kind of transmission line (or pseudo trans line) then some extra care is necessary.

The effect of a series resistor on the circuit performance may or not be significant.  For a line operated logic circuit (like 50 or 60Hz) it probably won't make much difference.

We might also mention the Schmitt Trigger input gate variations.  Sometimes they are used for timing and then there could be not only a resistor but also a capacitor.  The capacitor charge and/or discharge time sets the timing requirement.

[tggzzz]

For CMOS, if you were to use a resistor from the output of one gate to the input of another gate that would cause an extra undesirable propagation delay.

This is mostly true, but some CMOS is fast enough and some traces are long enough that putting a series resistor at the driver output (and perhaps an R/C termination at the end of the trace) is called for.  Not necessary in most cases, and I've designed plenty of fast designs with direct and unterminated connections, but we used to need to do this when using ECL logic (yes, I know that ECL is not CMOS), and some modern CMOS is just as fast as ECL.

And that begs the question: what does and does not constitute "long enough"? The answer is given in every text on transmission lines, so I'm not going to repeat it here.

I will, however, note that the key parameter is risetime, and with modern logic the lengths can be surprisingly short. And that's a key reason why the OP should start with "old" logic, 1980s vintage at latest.

[tggzzz]

Yes that's a good point.  If the output has to drive any kind of transmission line (or pseudo trans line) then some extra care is necessary.

The effect of a series resistor on the circuit performance may or not be significant.  For a line operated logic circuit (like 50 or 60Hz) it probably won't make much difference.

Er no.

If you violate the signal integrity requirements for a clock driving flip flops, then you are just as screwed at 1Hz as at 1GHz. Ditto violating the data's hold time.

Repeat after me: period is irrelevant, transition time is the only significant parameter

[tychob]

Is my math for the worst case for 74HC574 running at 5V (1980s vintage) correct, am I ignoring something? It feels worryingly fast:
It specifies a 3.5pF capacitive load, and the family is 35mA current, so the rise rate for a single load is 35/3.5 = 10V/ns or 400ps between 0.5V and 4.5V that current is specified for. By bogatins law, that is 0.8" or 2cm before transmission line effects come into play.

Or did you mean something even older like 74LS or 4000 as an appropriate family for a beginner.

[tggzzz]

 You can use measured risetime and capacitance to derive the current. You can't use capacitance plus maximum current to derive risetime, since something might limit the current (e.g. lead inductance, V vs I characteristics).

Calculating the current through the ground lead of an octal buffer where all outputs switch simultaneously is enlightening. Then work out the voltage drop across the lead inductance for that dI/dt.

Overall, 400ps would be an unrealistically fast risetime. Nonetheless calculations of this kind are a salutary eye opener

For any particular logic family, read the manufacturer's (or TI or NatSemi) application notes; that's why they are there!

With care and effort and modern 74LVC logic, I have driven a 50ohm line with <300ps risetime, https://www.eevblog.com/forum/testgear/show-us-your-square-wave/msg1902941/#msg1902941