EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: Saimoun on November 09, 2023, 04:28:40 pm
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Hi all :)
I'm quite new to circuit designing using gates IC (for example a NAND gate), I usually design with an MCU but I'm trying to implement logic without MCUs, using gates.
I could not find any "proper" examples of a schematic using those ICs (any gate IC).
My questions are:
- Should you use current limiting resistors on the gate's inputs?
- Should you make sure the gate's inputs are pulled low or high while the circuit starts up (using f.x. a 10k pull-down res)?
- Can you simply connect directly the output of one gate to the input of another?
- I assume decent decoupling for each gate IC is necessary on the power pins, just like with an MCU?
- What about considerations like rise-time and fall-time, should one add a low value (say 100pF) cap on the output of a gate?
And as I understood gates inputs are basically the "gate pin" of a Mosfet, and if I was using a Mosfet I would definitely use a current limiting resistor (to avoid having huge currents while the gate is charging) and a pulldown. Though in the few schematics I have seen - as I said it's hard to find any :-// - people seem to simply connect inputs and outputs without caring about these things.
Any thoughts?
Thank you :)
PS: this is what I'm trying to design: https://www.eevblog.com/forum/beginners/sending-a-digital-signal-with-an-rc-circuit/ (https://www.eevblog.com/forum/beginners/sending-a-digital-signal-with-an-rc-circuit/)
(but these questions are much more general about gates and has nothing to do as such with the project, so I thought it deserved a new topic)
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Should you use current limiting resistors on the gate's inputs?
No, your design would be a mess of resistors.
Should you make sure the gate's inputs are pulled low or high while the circuit starts up (using f.x. a 10k pull-down res)?
Only if it is not connected to anything else. If it is driven by the output of another gate, then don't worry about it.
Can you simply connect directly the output of one gate to the input of another?
You should do that.
I assume decent decoupling for each gate IC is necessary on the power pins, just like with an MCU?
Correct.
What about considerations like rise-time and fall-time, should one add a low value (say 100pF) cap on the output of a gate?
Don't do that.
And as I understood gates inputs are basically the "gate pin" of a Mosfet, and if I was using a Mosfet I would definitely use a current limiting resistor (to avoid having huge currents while the gate is charging) and a pulldown. Though in the few schematics I have seen - as I said it's hard to find any :-// - people seem to simply connect inputs and outputs without caring about these things.
The current will be limited by the driving ability of the output.
Don't overthink it, all commonly available logic devices are designed to be directly compatible with each other inputs and outputs.
You can also look at schematics from the time when designing with individual ICs was the norm. Find Commodore or Amiga schematics and you will see what they do there.
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Amazing, Alex, thanks so much for the reply - short and sweet!!
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Note that a lot of the really old stuff will be 74 or 74LS series, which nobody uses these days and which did have a few traps (74 series sourced significant current from the inputs when pulled low, and didn't pull high for toffee) so you did tend to see pullups and such there, this is where the led wired between an output and Vcc came from as the 74 and 74LS could pull down much better then they could pull up.
Slightly more modern logic designs using the 74HC and newer families don't need that stuff.
You do still sometimes see 4000 series which are high voltage cmos, anaemic output drive being the trap there, but it gets it done.
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Connecting gates from the same family (e.g., 74LS, 74HCT, 4000) is straightforward: the only question is "fanout", the number of inputs that can be driven from one output.
The original 7400 specs allowed a fanout of 10 (16 mA output sink current and 1.6 mA per input source current), but the other familes differ.
It gets more difficult when you need to connect an output from one family to an input from another family: then you have to read the datasheets to see what output voltages and currents are available from the source and what input voltage is required at the input (and what current that input requires).
For example, a pull-up resistor to Vcc may be needed on a TTL output to drive a CMOS input to a high-enough input voltage for noise immunity (depends on the CMOS family).
Connecting CMOS to CMOS, the DC currents at the inputs are negligible, but the total capacitance from multiple inputs connected together determines the current during the transition and possibly the transition time.
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Should you make sure the gate's inputs are pulled low or high while the circuit starts up (using f.x. a 10k pull-down res)?
Only if it is not connected to anything else. If it is driven by the output of another gate, then don't worry about it.
Generally true, but some logic devices have a "tri-state" output, and most uController I/O pins default to tri-state until otherwise configured. You probably want a pull-up or pull-down resistor (as appropriate) when a gate input is connected to a potentially tri-state output driver.
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Let's say you need a 32 bit register (program counter for uC). You could use 8 74ls74a chips with 14 pins each - total 112 pins and 224 connections (you have to wire both ends)
OR
You can instantiate the register with 1 line of VHDL and control it with as few as 3 lines.
Let me think...
If you screw up the design, it's a lot easier to edit a file than it is to tear down a bunch of wire wrap.
Think about how the wire wrap will be chained.
https://www.ti.com/lit/ds/symlink/sn74ls74a.pdf (https://www.ti.com/lit/ds/symlink/sn74ls74a.pdf)
I'll stick with FPGAs...
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And as I understood gates inputs are basically the "gate pin" of a Mosfet, and if I was using a Mosfet I would definitely use a current limiting resistor (to avoid having huge currents while the gate is charging) and a pulldown. Though in the few schematics I have seen - as I said it's hard to find any :-// - people seem to simply connect inputs and outputs without caring about these things.
Its all a matter of scale - CMOS logic gate FETs are absolutely tiny, current spikes on charging will be measure in a few mA at worst as the gate capacitance is pF or less (from the pin itself) and only fF internally (femtofarads). And logic gate outputs have significant series resistance, 100 ohms kind of value. Besides you want to charge those gate capacitances as hard as possible as that's the source of delay. Compared to a power MOSFET its roughly 4 orders of magnitude less capacitance and current...
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And as I understood gates inputs are basically the "gate pin" of a Mosfet, and if I was using a Mosfet I would definitely use a current limiting resistor (to avoid having huge currents while the gate is charging) and a pulldown. Though in the few schematics I have seen - as I said it's hard to find any :-// - people seem to simply connect inputs and outputs without caring about these things.
Its all a matter of scale - CMOS logic gate FETs are absolutely tiny, current spikes on charging will be measure in a few mA at worst as the gate capacitance is pF or less (from the pin itself) and only fF internally (femtofarads). And logic gate outputs have significant series resistance, 100 ohms kind of value. Besides you want to charge those gate capacitances as hard as possible as that's the source of delay. Compared to a power MOSFET its roughly 4 orders of magnitude less capacitance and current...
The output resistance depends on the logic family. For example The 74LVC1G* devices have an output resistance of around 7ohms. If you want them to drive a 50ohm line, series terminate them with 43ohms.
Similarly, the transient current will largely depend on the load capacitance.
To the OP...
The aim is electrically short wires directly connecting a logic output to logic inputs of the same family. The definition of "short" is determined solely by the transition time (i.e.edge speed) and the clock rate is completely irrelevant. Hence slower/older logic families can tolerate longer wires.
If the wire is not electrically short, then you have to treat it as a transition line, and that usually requires resistors. There are many text books and application notes defining what is clearly "short", "long", and the grey area in between. I'm not going to poorly recapitulate those excellent texts.
When it comes to constructing a circuit, you must realise that the devices are analogue circuits that interpret analogue voltage waveforms as digital signals. Ensuring the waveforms do not violate the requirements for correct interpretation is known as ensuring "signal integrity". The principal parameters are Vil, Vih, tsu and th. Those are best measured with a scope, using good probing practice. Also ensure all ground connections are as short as possible, preferably a ground plane. IMNSHO solderless breadboards cause many subtle problems for beginners.
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When it comes to constructing a circuit, you must realise that the devices are analogue circuits that interpret analogue voltage waveforms as digital signals. Ensuring the waveforms do not violate the requirements for correct interpretation is known as ensuring "signal integrity". The principal parameters are Vil, Vih, tsu and th. Those are best measured with a scope, using good probing practice. Also ensure all ground connections are as short as possible, preferably a ground plane. IMNSHO solderless breadboards cause many subtle problems for beginners.
What does a practical methodology of constructing a CPU design or other complex logic of some sort using some sort of MSI gate IC whilst being aware of grounding and signal integrity look like in the modern world? Perfboard/stripboard don't have ground planes. Matrix board is really hard to find documentation on how to use. And Manhattan has a combination of low density (how do you fit 50-100 chips on a manageable sheet?) combined with needing a lot of adapters if you aren't sicking with disappearing DIPs.
Is picking logic families like sticking with 4000 serial cmos an option to keep edge times low enough that transmission effects to a point you don't have to worry about them, even without a ground plane? Also when it comes to a scope. A typical beginner scope is 50-100MHz bandwidth. By the 0.35 rule, that means you can see transitions of 3.5 nanoseconds. How do you look at gate drive, gate capacitance, and Vil, Vih, tsu and th for a logic chip, and know that all the relevant signals and noise will be slower than that? Vs accidentally ending up with a logic family like 74G where its looks like its possible to violate the hold time, and not be able to see that on a affordable scope.
Or is the message to embrace unreliability and expect failure? Saying you must take into account "signal integrity" is all very well, but how does that translate into meaningful design rules, methodology or troubleshooting steps, other than just 'get a degree or deal with failure'?
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When it comes to constructing a circuit, you must realise that the devices are analogue circuits that interpret analogue voltage waveforms as digital signals. Ensuring the waveforms do not violate the requirements for correct interpretation is known as ensuring "signal integrity". The principal parameters are Vil, Vih, tsu and th. Those are best measured with a scope, using good probing practice. Also ensure all ground connections are as short as possible, preferably a ground plane. IMNSHO solderless breadboards cause many subtle problems for beginners.
What does a practical methodology of constructing a CPU design of some sort using some sort of MSI gate IC whilst being aware of grounding and signal integrity look like in the modern world? Perfboard/stripboard don't have ground planes. Matrix board is really hard to find documentation on how to use. And Manhattan has a combination of low density (how do you fit 50-100 chips on a manageable sheet?) combined with needing a lot of adapters if you aren't sicking with disappearing DIPs.
Is picking logic families like sticking with 4000 serial cmos an option to keep edge times low enough that transmission effects to a point you don't have to worry about them, even without a ground plane?
Or is the message to embrace unreliability and expect failure? Saying you must take into account "signal integrity" is all very well, but how does that translate into meaningful design rules, methodology or troubleshooting steps, other than just 'get a degree or deal with failure'?
The alternative to doing research and understanding the information in textbooks, magazines, and application notes has a name: "cargo cult engineering".
A craftsman understands what their tools can and can't do. A beginner has to be introduced where the dragons are hiding, so they might recognise them when they appear, and to avoid becoming demoralised by marginal pattern sensitive intermittent faults.I
Physics will win.
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The alternative to doing research and understanding the information in textbooks, magazines, and application notes has a name: "cargo cult engineering".
A craftsman understands what their tools can and can't do. A beginner has to be introduced where the dragons are hiding, so they might recognise them when they appear, and to avoid becoming demoralised by marginal pattern sensitive intermittent faults.I
Physics will win.
As opposed to being overwhelmed and demoralized by the variety of potential failure cases which may or may not happen to them? "cargo cult engineering" is not ideal, but beginners don't have the capability to actually engineer. A breadboard may be unreliable, but is it more unreliable than the thing that never got built because of analysis paralysis? I suppose that depends on whether you count consistently broken in a way that doesn't teach you anything as a reliable outcome. A thing that works most of the time is more an achievement and learning opportunity than a pile of books serving as a doorstop.
And sometimes the data needed for actual engineering as opposed to cargo cult rules just isn't available. Or could you point to a datasheet that explains why 100nF is the preferred value for decoupling 7400 series gates? As opposed to 10nF or 47nF or 470nF? Is 'always use a ground plane', without actually understanding the physics of the return currents, which you aren't going to internalise at the start, and arguable better internalized by doing a seperate ground return path for every signal, not also a cargo cult rule? For example, why doesn't ethernet need a groundplane that both sides are mounted on?
A master craftsman understands exactly what there tools can and can't do. An apprentice knows that there are large areas they don't know how to do yet, but if they follow the specific steps from the master, they can replicate the results. A good workflow for an apprentice is one where the vast majority is fixed for them, with a small focused area that they can expand at any one time, rather than expecting them to research everything.
Physics will win, so beginners need managable abstractions/models over physics that aren't fully internalize maxwells equations. So as a master, rather than just saying don't do X, could you direct us to things we should do instead? Do you need to do a finite element analysis simulation of microwave effects before you connect an LED, resistor and battery?
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The first step is to realize that most types of digital design layout are actually pretty easy. Use medium-speed CMOS logic where you can, and keep the connections fairly short and use lots of power bypass capacitors. Use series source terminations on the longer connections. Be aware of clock / data skew issues. It's going to work, or if it doesn't it's probably a logic error, not a layout issue. I've designed 10 GBit fiber-optic systems, and used breadboards to test simple uController designs. 10 GBit stuff needs careful design and layout, but the lower-speed circuitry can be quite forgiving.
So I'm with tychob on this: Don't be afraid -- just jump in.
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Here is my 2c:
- You can find lots of circuits in manufacturers' databooks and application notes, and hobby electronics magazines.
- Use CMOS family of logic gates, so you do not need to use resistors between outputs and inputs because the CMOS logic's input current is typicaöly very low. Also, CMOS logic consumes little power compared to older TTL-logic families.
- Try to avoid the fastest CMOS logic families, as they make decoupling and maintaining signal integrity much harder.
- Use decoupling capacitors between power supply (VDD) and ground (GND), and place these capacitors near the ICs power supply pins.
- Connect any unused CMOS logic input either to VDD or GND. Use a resistors so that you can add bodge wires easier if you need to modify the circuit at some point during development and testing.
- You can use zero ohm resistors between outputs and inputs if you want, as the may help with probing the circuit and make adding bodge wires easier if needed.
- If you have a fast signal rise or fall times, and you need to make a long wiring or have a long wire on a pcb, you may need to consider impedance matching in order to avoid ringing and thus maintaining signal integrity. A simple impedance matching can be made using a series termination: place a suitable resistor close to the output pin in series with the signal. If the output is driving two or more long lines, you need to use one resistor for each signal (ie. one output is connected to multiple resistors, and each resistor is connected to only one signal wire).
- If you connect multiple inputs to a single output with fast rise and fall times, you may need to consider fanout capabilities of the output pin because the CMOS inputs are typically capacitive.
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I think most of it has been said above. I would only add that there are/were "Cookbook"s by Don Lancaster for at least TTL and CMOS logic use/design. They were great for beginners. You can probably find them on E-Bay and perhaps other such forums. You might consider buying one or more of them.
https://www.ebay.com/sch/i.html?_from=R40&_trksid=p4432023.m570.l1313&_nkw=TTL+Cookbook&_sacat=0 (https://www.ebay.com/sch/i.html?_from=R40&_trksid=p4432023.m570.l1313&_nkw=TTL+Cookbook&_sacat=0)
https://www.ebay.com/sch/i.html?_from=R40&_trksid=p2334524.m570.l1313&_nkw=CMOS+Cookbook&_sacat=0&LH_TitleDesc=0&_odkw=TTL+Cookbook&_osacat=0 (https://www.ebay.com/sch/i.html?_from=R40&_trksid=p2334524.m570.l1313&_nkw=CMOS+Cookbook&_sacat=0&LH_TitleDesc=0&_odkw=TTL+Cookbook&_osacat=0)
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Let's say you need a 32 bit register (program counter for uC). You could use 8 74ls74a chips with 14 pins each - total 112 pins and 224 connections (you have to wire both ends)
OR
You can instantiate the register with 1 line of VHDL and control it with as few as 3 lines.
Let me think...
If you screw up the design, it's a lot easier to edit a file than it is to tear down a bunch of wire wrap.
Think about how the wire wrap will be chained.
https://www.ti.com/lit/ds/symlink/sn74ls74a.pdf (https://www.ti.com/lit/ds/symlink/sn74ls74a.pdf)
I'll stick with FPGAs...
While those advantages are real, there are corresponding disadvantages.
Modern tool chains are very complex, there is a steep learning curve that must be climbed before gratifying results are obtained.
Learning the concepts of HDL such as Verilog and VHDL is useful and will last a lifetime. Learning which buttons to press is boring and will be outdated within a few years.
If someone is aiming to become an electronic engineer specialising in digital circuits, learning an HDL is well worth the time and effort. But for a beginner taking their first steps it is probably better to use an old slow logic family.
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What hasn’t been particularly mentioned is to use simulation software in order to experiment without risking damage to parts, or wasting time with breadboards or similar.
My favourite software is Tina, I only have the student version, but that is good enough for most purposes. https://www.tina.com/ (https://www.tina.com/)
Another popular one is Logisim, free from:
https://sourceforge.net/projects/circuit/ (https://sourceforge.net/projects/circuit/)
With a breadboard you can try your circuit, beware that long leads and less than ideal layout will produce some ringing, overshoot and other “less than perfect” waveforms. Also because we are dealing with square waves (or short pulses), you need several times the bandwidth to display them well on an oscilloscope.
Regarding which type of logic to use, check suppliers and manufacturers data sheets in order to avoid picking obsolete or very expensive parts. Some are hard to find in DIL form (through hole, fits in IC socket). Old books and magazines will refer to 74, 74LS, etc. these have been superseded.
More common in recent times are 74HC ICs, I’ve used 74HC series in a GPS disciplined oscillator on a fairly sloppy board layout without a problem. The signals are 10 MHz, 5 MHz, 1 MHz and one pulse per second. Control is with an Arduino Nano. Other builders seem to have even used perf board. The project is described here:
https://www.qsl.net/zl1bpu/PROJ/NGPSDO/Dividers.htm (https://www.qsl.net/zl1bpu/PROJ/NGPSDO/Dividers.htm)
SJ
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With a breadboard you can try your circuit, beware that long leads and less than ideal layout will produce some ringing, overshoot and other “less than perfect” waveforms. Also because we are dealing with square waves (or short pulses), you need several times the bandwidth to display them well on an oscilloscope.
Yes, except "several times the bandwidth" is a classic misunderstatement that catches out the unwary.
The required bandwidth solely depends on the rise/fall time; the period is completely irrelevant. Anthropomorphic explanation: the devices and interconnections neither "know" nor "care" when the next transition will occur.
If you doubt that, consider the 1pps (i.e. 1Hz) pulse output from a GPSDO etc. If you think 2,3,10,100.. Hz is sufficient, then can I interest you in buying a bridge I have for sale :)
For a little theory and some practical measurements, see https://entertaininghacks.wordpress.com/2018/05/08/digital-signal-integrity-and-bandwidth-signals-risetime-is-important-period-is-irrelevant/ Some people are surprised by what is demonstrated there.
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Search old implementations of GPIB.
There you have gates section of various types and their connections to outer world.
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How about getting a broken old freq counter and fixing it?
You would get to understand how the ICs are laid out and what they do. Like the location of decoupling caps and their values....
These things are not horribly complicated and can be obtained cheaply. Something like an old Heathkit. (they are good counters for their era)
Suggestions on building your own design:
Use middle of the road chips, CMOS, that are not extremely fast.
Use sockets for the chips.
When ordering chips, order more than you need (for the next project)
Sockets are great for repair because you may not be able to locate the exact fault right away and then you can put the original chip back in without much work.
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The required bandwidth solely depends on the rise/fall time; the period is completely irrelevant. Anthropomorphic explanation: the devices and interconnections neither "know" nor "care" when the next transition will occur.
Except what matters is not the rise time that is output, but do you meet the minimum rise fall time at the input. And that can be surprisingly large. A 74HC00 has a minimum risefall time of 50us. A 74HC08 is specified to 80ns. So your edge can be filtered to 5MHz, and that's not going to cause an actual issue on the inputs. So long as you aren't running a system anywhere near f_max and you follow synchronous design practises, then ringing induced glitches aren't going to cause you actual problems, (because sampling time), and for overshoot, the protection diodes are specified to be able to take up to 20mA of that. So unless you are driving hard and fast, none of these are actually necessarily problems. And if you are driving hard and fast, your clock edge is probably at least good 10% of your clock period, because anything less would be inefficient, so the rise/fall vs clock frequency becomes less relevant.
So long as power is well decoupled, and the clocks are clean enough to remain monotonic, then synchronous digital logic is remarkably robust to bad signal integrity on the data paths, if the clock sampling frequency is sufficiently below the design speed f_max to allow time for ringing glitches to propagate out.
Unless your view is that beginners should just not try and build digital logic? Since 4ns typical outputs are specified for a 74HC00, which translates to 87.5MHz by the rule, or more importantly: An entry level scope can't see any harmonics at this speed to tell you if your integrity is any good.
Use sockets for the chips.
When ordering chips, order more than you need (for the next project)
Sockets are great for repair because you may not be able to locate the exact fault right away and then you can put the original chip back in without much work.
Do you have a good source for sockets for SOIC, TSSOP, and SOT packages?
What hasn’t been particularly mentioned is to use simulation software in order to experiment without risking damage to parts, or wasting time with breadboards or similar.
It depends on what your goal is. If you want to learn industrial digital design, VHDL/Verilog is worth learning with a FPGA. If you just want to fiddle with logic theory, simulators can get a start, but it is hard to get anywhere and really feels pointless (if you want abstract logic, programming is a more useful skill). If you want to get over the barrier of actually doing digital circuitry, none of the simulated options will teach you the impact of actually building something and the circuitry involved.
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The required bandwidth solely depends on the rise/fall time; the period is completely irrelevant. Anthropomorphic explanation: the devices and interconnections neither "know" nor "care" when the next transition will occur.
Except what matters is not the rise time that is output, but do you meet the minimum rise fall time at the input. And that can be surprisingly large. A 74HC00 has a minimum risefall time of 50us. A 74HC08 is specified to 80ns. So your edge can be filtered to 5MHz, and that's not going to cause an actual issue on the inputs.
The particular times you mention are not relevant to the context in which I made the statement - and which you chose to omit. To that extent your response is a strawman argument.
Apart from that, thank you for emphasising the point I made and you quoted. There's no "except" about it!
So long as you aren't running a system anywhere near f_max and you follow synchronous design practises, then ringing induced glitches aren't going to cause you actual problems, (because sampling time), and for overshoot, the protection diodes are specified to be able to take up to 20mA of that. So unless you are driving hard and fast, none of these are actually necessarily problems.
So long as power is well decoupled, and the clocks are clean enough to remain monotonic, then synchronous digital logic is remarkably robust to bad signal integrity on the data paths, if the clock sampling frequency is sufficiently below the design speed f_max to allow time for ringing glitches to propagate out.
It would have been better for a beginner if you explicitly addressed the point you explicitly excluded: signal integrity on the clock line.
That is a classic problem area, especially if poor construction allows non-monotonic clock transitions. I've seen many beginner's constructions have problems like that.
Signal integrity on data lines is, of course, far less demanding. That's a key advantage of clocked designs.
Unless your view is that beginners should just not try and build digital logic? Since 4ns typical outputs are specified for a 74HC00, which translates to 87.5MHz by the rule, or more importantly: An entry level scope can't see any harmonics at this speed to tell you if your integrity is any good.
Strawman argument, therefore I'm not going to respond.
Please do not take statements out of context, and please do not invent points I haven't and wouldn't make.
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So long as you aren't running a system anywhere near f_max and you follow synchronous design practises, then ringing induced glitches aren't going to cause you actual problems, (because sampling time), and for overshoot, the protection diodes are specified to be able to take up to 20mA of that. So unless you are driving hard and fast, none of these are actually necessarily problems.
So long as power is well decoupled, and the clocks are clean enough to remain monotonic, then synchronous digital logic is remarkably robust to bad signal integrity on the data paths, if the clock sampling frequency is sufficiently below the design speed f_max to allow time for ringing glitches to propagate out.
It would have been better for a beginner if you explicitly addressed the point you explicitly excluded: signal integrity on the clock line.
That is a classic problem area, especially if poor construction allows non-monotonic clock transitions. I've seen many beginner's constructions have problems like that.
Signal integrity on data lines is, of course, far less demanding. That's a key advantage of clocked designs.
To focus on this then, what construction practices do prevent double clocking? One thing I have thought about in theory but not tried is distributing the clock to dedicated flipflop modules by coax. But I know I have no where near enough knowledge to actually advise here. What affordable to a beginner tooling allows diagnoses of double clocking to a chip with a >=100MHz analogue clock input bandwidth? Or on the opposite side, which logic families have less than 100MHz analogue bandwidth on the clock inputs? I excluded it because its still an open question to me with the only answer I have found for myself being 'hope and pray' or 'cargo cult', not exactly engineering.
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200MHz+ 'scope will help diagnose signal integrity problems, especially with a 5k:50R divider, ie 5k resistor on the end of some 50 ohm coax, with 50 ohm load at the scope-end - such a low-impedance probe is more faithful to the actual voltages, especially if the probe ground lead is short and direct (low inductance).
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The "X with analogue bandwidth of Y" is, of course a question based on an inaccurate premise. The transition time is what matters. I suggest you read the references I gave earlier in this thread, search for Bogotins rules of thumb, and read manufacturers application notes.
I wouldn't bother with coax; for critical lines and slow/medium speed logic twisted pair is equivalent.
It is usually easiest to base a prototype on a solid ground plane, and keep wires close to the plane. Failing that, approximate a ground plane by having a grid of wires that approximate a ground plane.
Once you understand the theory, you will be able to understand what you can (and can't) get away with in practice. In the absence of that, use short wires over a ground plane.
For examples of old and new techniques, see https://entertaininghacks.wordpress.com/2020/07/22/prototyping-circuits-easy-cheap-fast-reliable-techniques/
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200MHz+ 'scope will help diagnose signal integrity problems, especially with a 5k:50R divider, ie 5k resistor on the end of some 50 ohm coax, with 50 ohm load at the scope-end - such a low-impedance probe is more faithful to the actual voltages, especially if the probe ground lead is short and direct (low inductance).
Yes. Such low impedance resistive divider Z0 probes have a higher tip impedance than the traditional 10Mohm "high" impedance probes. Fundamental principle is that they have lower tip capacitance, so load the circuit less and self-resonate at higher frequencies.
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The "X with analogue bandwidth of Y" is, of course a question based on an inaccurate premise. The transition time is what matters. I suggest you read the references I gave earlier in this thread, search for Bogotins rules of thumb, and read manufacturers application notes.
Analogue bandwidth is an important value. Because thats how an oscilloscope front end is specified. And a big part of the question here is: If I have X oscilloscope, and Y logic gate, where Y gate does not specify a minimum rise time, only a minimum time between edges to have an effect, how can I be confident that the oscilloscope will see any noise that would trigger the gate?
That 0.35 magic number after all is a characterization of the oscilloscope front end.
I wouldn't bother with coax; for critical lines and slow/medium speed logic twisted pair is equivalent.
It is usually easiest to base a prototype on a solid ground plane, and keep wires close to the plane. Failing that, approximate a ground plane by having a grid of wires that approximate a ground plane.
Once you understand the theory, you will be able to understand what you can (and can't) get away with in practice. In the absence of that, use short wires over a ground plane.
For examples of old and new techniques, see https://entertaininghacks.wordpress.com/2020/07/22/prototyping-circuits-easy-cheap-fast-reliable-techniques/
Why are twisted pairs sufficient, why a ground plane? In the absence of actual understanding, I'm faced with a bunch of 'cargo cult' rules. I'd like to see somewhere I can read more on how to achieve reliable clock distribution on manhatten, because I can't seem to find anything that isn't in one of the extremes of 'just use a breadboard', or 'keep the clock to a dedicated PCB devboard'. Or even just some more resources on things like how to attach adapters so they are grounded appropriately. Theres plenty of resources on how to use strip board or breadboards without a ground plane.
200MHz+ 'scope will help diagnose signal integrity problems, especially with a 5k:50R divider, ie 5k resistor on the end of some 50 ohm coax, with 50 ohm load at the scope-end - such a low-impedance probe is more faithful to the actual voltages, especially if the probe ground lead is short and direct (low inductance).
And where does one find an affordable 200MHz scope? An older DSO?
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What textbooks on logic system design and construction have you consulted?
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What textbooks on logic system design and construction have you consulted?
Which textbooks would you recommend that include practical, mechanical construction advice? Because so far I've been limited to app notes and online sources.
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My textbooks are not up-to-date on high-speed digital construction.
You might start with the usual suspect, "Art of Electronics" by Horowitz and Hill.
Look at the current edition at your local library, and see how much of your concerns are covered, then look at the references to cover other details.
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The "X with analogue bandwidth of Y" is, of course a question based on an inaccurate premise. The transition time is what matters. I suggest you read the references I gave earlier in this thread, search for Bogotins rules of thumb, and read manufacturers application notes.
Analogue bandwidth is an important value. Because thats how an oscilloscope front end is specified. And a big part of the question here is: If I have X oscilloscope, and Y logic gate, where Y gate does not specify a minimum rise time, only a minimum time between edges to have an effect, how can I be confident that the oscilloscope will see any noise that would trigger the gate?
That 0.35 magic number after all is a characterization of the oscilloscope front end.
Sigh.
My latest scope puts its principal specification on the front panel: 200ps risetime. The corresponding 1.7GHz is buried in the manual, since it is unimportant.
I wouldn't bother with coax; for critical lines and slow/medium speed logic twisted pair is equivalent.
It is usually easiest to base a prototype on a solid ground plane, and keep wires close to the plane. Failing that, approximate a ground plane by having a grid of wires that approximate a ground plane.
Once you understand the theory, you will be able to understand what you can (and can't) get away with in practice. In the absence of that, use short wires over a ground plane.
For examples of old and new techniques, see https://entertaininghacks.wordpress.com/2020/07/22/prototyping-circuits-easy-cheap-fast-reliable-techniques/
Why are twisted pairs sufficient, why a ground plane? In the absence of actual understanding, I'm faced with a bunch of 'cargo cult' rules. I'd like to see somewhere I can read more on how to achieve reliable clock distribution on manhatten, because I can't seem to find anything that isn't in one of the extremes of 'just use a breadboard', or 'keep the clock to a dedicated PCB devboard'. Or even just some more resources on things like how to attach adapters so they are grounded appropriately. Theres plenty of resources on how to use strip board or breadboards without a ground plane.
Read the resources mentioned. Then ask a question based on what you have learned.
200MHz+ 'scope will help diagnose signal integrity problems, especially with a 5k:50R divider, ie 5k resistor on the end of some 50 ohm coax, with 50 ohm load at the scope-end - such a low-impedance probe is more faithful to the actual voltages, especially if the probe ground lead is short and direct (low inductance).
And where does one find an affordable 200MHz scope? An older DSO?
On fleabay or at a hamfest. My latest one cost £25. I wouldn't recommend that path to a beginner, except where they are sure the scope is working correctly.
Older DSOs suck rocks and should be avoided like the plague. Exception: capturing single-shot events. Until the last decade they had many characteristics that fooled beginners and annoyed professionals. They were, however, mostly better than analogue storage scopes.
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What textbooks on logic system design and construction have you consulted?
Which textbooks would you recommend that include practical, mechanical construction advice? Because so far I've been limited to app notes and online sources.
Which ones have you read, and what have you learned from them?
It sounds like you want to avoid understanding theory. If that is the case then you will be limited to doing "monkey-see monkey-do" work.
Having said that, some of these might be relevant: https://entertaininghacks.wordpress.com/library-2/bookshelf/
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What textbooks on logic system design and construction have you consulted?
Which textbooks would you recommend that include practical, mechanical construction advice? Because so far I've been limited to app notes and online sources.
Which ones have you read, and what have you learned from them?
It sounds like you want to avoid understanding theory. If that is the case then you will be limited to doing "monkey-see monkey-do" work.
Having said that, some of these might be relevant: https://entertaininghacks.wordpress.com/library-2/bookshelf/
Its not that I want to avoid it, so much as my experience so far is that every time I make one step forward in learning theory, I learn two new things I still need to know before I understand. My current projection is a decade to actually understand enough theory. So I'm looking for a path that does allow making things before finishing that. Because I don't think trying to learn the equivelent of an EE degree on my own with no support and limited time is something I can manage. And at the moment, all I see are cargo cult and embracing unreliability.
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...my experience so far is that every time I make one step forward in learning theory, I learn two new things I still need to know before I understand. My current projection is a decade to actually understand enough theory.
You are simultaneously too optimistic and too pessimistic.
The "learn one thing discover two things you don't know" is real, and everybody experiences it. It is neverending. That's a principal joy of any intellectual profession.
Who the hell wants to be doing the same thing for the rest of their life?! And in addition anybody who thinks it will be possible is destined to be thrown on the scrap heap in a couple of decades.
The concept of "The Red Susan's Race" is as valid now as it was in 1865. Deal with it!
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So long as you aren't running a system anywhere near f_max and you follow synchronous design practises, then ringing induced glitches aren't going to cause you actual problems, (because sampling time), and for overshoot, the protection diodes are specified to be able to take up to 20mA of that. So unless you are driving hard and fast, none of these are actually necessarily problems.
So long as power is well decoupled, and the clocks are clean enough to remain monotonic, then synchronous digital logic is remarkably robust to bad signal integrity on the data paths, if the clock sampling frequency is sufficiently below the design speed f_max to allow time for ringing glitches to propagate out.
It would have been better for a beginner if you explicitly addressed the point you explicitly excluded: signal integrity on the clock line.
That is a classic problem area, especially if poor construction allows non-monotonic clock transitions. I've seen many beginner's constructions have problems like that.
Signal integrity on data lines is, of course, far less demanding. That's a key advantage of clocked designs.
To focus on this then, what construction practices do prevent double clocking? One thing I have thought about in theory but not tried is distributing the clock to dedicated flipflop modules by coax.
Double-clocking is potentially an issue, but I suspect not for the reasons you are thinking of. I've never seen a case of double clocking because a transmission line wasn't uses.
I'd be far more concerned that double-clocking might occur because of ground bounce in either the tx or rx, or - where the ground plane is insufficient - in some nearby but apparently unrelated buffer/line driver. There's a more probable cause of flip flop misbehaviour which might be incorrectly assigned to double clocking.
Most beginners concentrate on a flip-flop's setup time, since that directly affects the circuits "headline advertised" max speed. But if inadequate setup time is a possibility, it can easily be tested by slightly reducing the clock frequency and seeing if the problem disappears.
But there's another requirement for correct flip-flop behaviour: the hold time. The hold time is (in practice) noticeably shorter than the setup time. Importantly, in any given circuit reducing the clock frequency will not improve the hold time. To emphasise that, if you have a marginal failure with a 10MHz clock, you will still have the same marginal failure with a 1Hz clock.
That ties in with why, when considering signal integrity, thinking in terms of a digital system's clock frequency is simply wrong.
Now consider a clock line with poor signal integrity. If the edge is non-monotonic, it will be slower and that will erode the hold time.
Ground bounce can have the same consequences.
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Have you Googled 'high speed digital logic physical layout'? There might be some useful information.
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There's lots of information. Much of it contradictory. Much of it directly contradicts what has already been said in this thread. Much of it has way too much assumed theory knowledge to be usable by someone who struggles with the implications of transmission line theory, let alone a beginner who doesn't know what a transmission line is yet. Useful trustworthy and understandable information? Much harder to find.
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There's lots of information. Much of it contradictory. Much of it directly contradicts what has already been said in this thread. Much of it has way too much assumed theory knowledge to be usable by someone who struggles with the implications of transmission line theory, let alone a beginner who doesn't know what a transmission line is yet. Useful trustworthy and understandable information? Much harder to find.
The fundamentals aren't contradictory. OTOH the application of the fundamentals to one situation might be completely different to another situation. That might appear contradictory.
When I was young information was hard to acquire. Hobbyist magazines (with very variable quality), books from a bookshop (few, most with superficial indotmation and many gaps), books from the library (read a catalogue, wait a month). Consequently the key skill was the read carefully multiple times to extract everything.
Now data is trivial to acquire, and the key skill is to rapidly determine what should be ignored.
That will only get worse with websites created by LLMs; I've already noticed that happening and getting high up in a gurgle search.
That will only get worse since anybody can proclaim themselves an expert and disseminate their misunderstandings. See Yooootooob for examples.
Welcome to the modern world.
I suspect you are watching too many yoootooob vids, and odd blogs braindumps, and forums where random people give half-baked explanations.
So, do the hard work to read textbooks to understand the theory; there is no substitute. Read application notes to understand application of theory.
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For a book that is a good mix of theory and 'rules of thumb' that can be applied without needing to understand Heaviside (He was robbed by Maxwell!), take a look at "High speed signal propagation - advanced black magic', it hits a nice Balance IMHO.
Regards, Dan.
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For a book that is a good mix of theory and 'rules of thumb' that can be applied without needing to understand Heaviside (He was robbed by Maxwell!), take a look at "High speed signal propagation - advanced black magic', it hits a nice Balance IMHO.
Regards, Dan.
I've pointed him towards a set of books I have found useful over the years, one of which is clearly directly relevant to his current situation. I haven't seen any indication that he has looked at the list let alone a book.
He has been refreshingly open about his current situation here: https://www.eevblog.com/forum/beginners/circuit-design-with-logic-gates-in-practice/msg5165619/#msg5165619 (https://www.eevblog.com/forum/beginners/circuit-design-with-logic-gates-in-practice/msg5165619/#msg5165619)
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For learning digital logic "old school" style (without FPGA or CPLD) I would use SPLD, for example ATF16v8 or ATF22v10
Just buy bunch or them in DIP package and always install in sockets. Easy to reuse in your next project, simple language, easy PCB routing.
Can buy them new or second hand. Latest version of TL866 can program them, or you can make programmer yourself (google afterburner)
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Hi all :)
I'm quite new to circuit designing using gates IC (for example a NAND gate), I usually design with an MCU but I'm trying to implement logic without MCUs, using gates.
I could not find any "proper" examples of a schematic using those ICs (any gate IC).
My questions are:
- Should you use current limiting resistors on the gate's inputs?
- Should you make sure the gate's inputs are pulled low or high while the circuit starts up (using f.x. a 10k pull-down res)?
- Can you simply connect directly the output of one gate to the input of another?
- I assume decent decoupling for each gate IC is necessary on the power pins, just like with an MCU?
- What about considerations like rise-time and fall-time, should one add a low value (say 100pF) cap on the output of a gate?
And as I understood gates inputs are basically the "gate pin" of a Mosfet, and if I was using a Mosfet I would definitely use a current limiting resistor (to avoid having huge currents while the gate is charging) and a pulldown. Though in the few schematics I have seen - as I said it's hard to find any :-// - people seem to simply connect inputs and outputs without caring about these things.
Any thoughts?
Thank you :)
PS: this is what I'm trying to design: https://www.eevblog.com/forum/beginners/sending-a-digital-signal-with-an-rc-circuit/ (https://www.eevblog.com/forum/beginners/sending-a-digital-signal-with-an-rc-circuit/)
(but these questions are much more general about gates and has nothing to do as such with the project, so I thought it deserved a new topic)
Hello,
Most logic gate technology is made to be connected to another input without an issue.
For CMOS, if you were to use a resistor from the output of one gate to the input of another gate that would cause an extra undesirable propagation delay.
There are some other rules you should obey such as power supply bypassing and stuff like that though.
For the design implementation, you could design the circuit ad-hoc and then use Boolean Algebra to reduce the circuit to a minimum configuration of gates.
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Amazing guys, thank you all for the long list of info and the debate in this topic :)
I have my answers, but feel free to keep the debate going without me ;D
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Here are few pdf books you can get for free. TI, Nexperia, Onsemi etc have stacks of logic design notes.
https://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwiKru_HxsuCAxXEWUEAHfqMClEQFnoECBIQAQ&url=https%3A%2F%2Fmrcet.com%2Fdownloads%2Fdigital_notes%2FIT%2FDIGITAL%2520LOGIC%2520DESIGN%2520(R17A0461).pdf&usg=AOvVaw3uP434gzTyaTU1cNQpfb65&opi=89978449 (https://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwiKru_HxsuCAxXEWUEAHfqMClEQFnoECBIQAQ&url=https%3A%2F%2Fmrcet.com%2Fdownloads%2Fdigital_notes%2FIT%2FDIGITAL%2520LOGIC%2520DESIGN%2520(R17A0461).pdf&usg=AOvVaw3uP434gzTyaTU1cNQpfb65&opi=89978449)
https://www.google.co.uk/url?sa=i&url=http%3A%2F%2Fbitsavers.informatik.uni-stuttgart.de%2Fcomponents%2Fti%2F_dataBooks%2F1988_TI_Advanced_CMOS_Logic_Designers_Handbook.pdf&psig=AOvVaw12WLeLkiEQ5_fL6pkWDSEz&ust=1700327717528000&source=images&cd=vfe&opi=89978449&ved=0CBQQjhxqFwoTCMjL8cPEy4IDFQAAAAAdAAAAABAD (https://www.google.co.uk/url?sa=i&url=http%3A%2F%2Fbitsavers.informatik.uni-stuttgart.de%2Fcomponents%2Fti%2F_dataBooks%2F1988_TI_Advanced_CMOS_Logic_Designers_Handbook.pdf&psig=AOvVaw12WLeLkiEQ5_fL6pkWDSEz&ust=1700327717528000&source=images&cd=vfe&opi=89978449&ved=0CBQQjhxqFwoTCMjL8cPEy4IDFQAAAAAdAAAAABAD)
https://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwiSyKWRxsuCAxXgXUEAHVL-PGAQFnoECBQQAQ&url=https%3A%2F%2Farchive.org%2Fdownload%2FDigitalLogicAndComputerDesignByM.MorrisMano2ndEdition%2FDigital%2520Logic%2520And%2520Computer%2520Design%2520By%2520M.%2520Morris%2520Mano%2520%25282nd%2520Edition%2529.pdf&usg=AOvVaw0bEHRcdIwKEfYTi30lJmMB&opi=89978449 (https://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwiSyKWRxsuCAxXgXUEAHVL-PGAQFnoECBQQAQ&url=https%3A%2F%2Farchive.org%2Fdownload%2FDigitalLogicAndComputerDesignByM.MorrisMano2ndEdition%2FDigital%2520Logic%2520And%2520Computer%2520Design%2520By%2520M.%2520Morris%2520Mano%2520%25282nd%2520Edition%2529.pdf&usg=AOvVaw0bEHRcdIwKEfYTi30lJmMB&opi=89978449)
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For CMOS, if you were to use a resistor from the output of one gate to the input of another gate that would cause an extra undesirable propagation delay.
This is mostly true, but some CMOS is fast enough and some traces are long enough that putting a series resistor at the driver output (and perhaps an R/C termination at the end of the trace) is called for. Not necessary in most cases, and I've designed plenty of fast designs with direct and unterminated connections, but we used to need to do this when using ECL logic (yes, I know that ECL is not CMOS), and some modern CMOS is just as fast as ECL.
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For CMOS, if you were to use a resistor from the output of one gate to the input of another gate that would cause an extra undesirable propagation delay.
This is mostly true, but some CMOS is fast enough and some traces are long enough that putting a series resistor at the driver output (and perhaps an R/C termination at the end of the trace) is called for. Not necessary in most cases, and I've designed plenty of fast designs with direct and unterminated connections, but we used to need to do this when using ECL logic (yes, I know that ECL is not CMOS), and some modern CMOS is just as fast as ECL.
Hi,
Yes that's a good point. If the output has to drive any kind of transmission line (or pseudo trans line) then some extra care is necessary.
The effect of a series resistor on the circuit performance may or not be significant. For a line operated logic circuit (like 50 or 60Hz) it probably won't make much difference.
We might also mention the Schmitt Trigger input gate variations. Sometimes they are used for timing and then there could be not only a resistor but also a capacitor. The capacitor charge and/or discharge time sets the timing requirement.
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For CMOS, if you were to use a resistor from the output of one gate to the input of another gate that would cause an extra undesirable propagation delay.
This is mostly true, but some CMOS is fast enough and some traces are long enough that putting a series resistor at the driver output (and perhaps an R/C termination at the end of the trace) is called for. Not necessary in most cases, and I've designed plenty of fast designs with direct and unterminated connections, but we used to need to do this when using ECL logic (yes, I know that ECL is not CMOS), and some modern CMOS is just as fast as ECL.
And that begs the question: what does and does not constitute "long enough"? The answer is given in every text on transmission lines, so I'm not going to repeat it here.
I will, however, note that the key parameter is risetime, and with modern logic the lengths can be surprisingly short. And that's a key reason why the OP should start with "old" logic, 1980s vintage at latest.
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Yes that's a good point. If the output has to drive any kind of transmission line (or pseudo trans line) then some extra care is necessary.
The effect of a series resistor on the circuit performance may or not be significant. For a line operated logic circuit (like 50 or 60Hz) it probably won't make much difference.
Er no.
If you violate the signal integrity requirements for a clock driving flip flops, then you are just as screwed at 1Hz as at 1GHz. Ditto violating the data's hold time.
Repeat after me: period is irrelevant, transition time is the only significant parameter :)
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Is my math for the worst case for 74HC574 running at 5V (1980s vintage) correct, am I ignoring something? It feels worryingly fast:
It specifies a 3.5pF capacitive load, and the family is 35mA current, so the rise rate for a single load is 35/3.5 = 10V/ns or 400ps between 0.5V and 4.5V that current is specified for. By bogatins law, that is 0.8" or 2cm before transmission line effects come into play.
Or did you mean something even older like 74LS or 4000 as an appropriate family for a beginner.
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You can use measured risetime and capacitance to derive the current. You can't use capacitance plus maximum current to derive risetime, since something might limit the current (e.g. lead inductance, V vs I characteristics).
Calculating the current through the ground lead of an octal buffer where all outputs switch simultaneously is enlightening. Then work out the voltage drop across the lead inductance for that dI/dt.
Overall, 400ps would be an unrealistically fast risetime. Nonetheless calculations of this kind are a salutary eye opener :)
For any particular logic family, read the manufacturer's (or TI or NatSemi) application notes; that's why they are there!
With care and effort and modern 74LVC logic, I have driven a 50ohm line with <300ps risetime, https://www.eevblog.com/forum/testgear/show-us-your-square-wave/msg1902941/#msg1902941 (https://www.eevblog.com/forum/testgear/show-us-your-square-wave/msg1902941/#msg1902941)
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I love the way this "beginners" board launches into the "need" for $10,000, $25,000, or $100,000 worth of test equipment.
I have designed, built, and placed in daily service in commercial facilities, circuits that were based on discrete logic chips using switches, resistors, and analog VOMs for my design lab equipment. It can be done with $25 worth of equipment, for Pete's sake. I still don't have even $2000 worth of equipment but would not hesitate to start on almost any design you can imagine at the beginner or intermediate level. Or even 90% of designs at the advanced level.
One of these types of breadboards is nice to have. They come in many styles and sizes and prices: this is only one example.
https://www.amazon.com/BB400-Solderless-Plug-BreadBoard-tie-points/dp/B0040Z1ERO/ref=asc_df_B0040Z1ERO/?tag=hyprod-20&linkCode=df0&hvadid=241888066999&hvpos=&hvnetw=g&hvrand=3481730356964540888&hvpone=&hvptwo=&hvqmt=&hvdev=c&hvdvcmdl=&hvlocint=&hvlocphy=9027887&hvtargid=pla-638906394402&psc=1&mcid=df8a82d513d937b38ac19209b20d38be&gclid=Cj0KCQiA3uGqBhDdARIsAFeJ5r2Bf3Hn9BAFTkkVJRDWo13Jtzo2joT1CvOYTTWmDM07E5Ru6yNsvNMaAuECEALw_wcB (https://www.amazon.com/BB400-Solderless-Plug-BreadBoard-tie-points/dp/B0040Z1ERO/ref=asc_df_B0040Z1ERO/?tag=hyprod-20&linkCode=df0&hvadid=241888066999&hvpos=&hvnetw=g&hvrand=3481730356964540888&hvpone=&hvptwo=&hvqmt=&hvdev=c&hvdvcmdl=&hvlocint=&hvlocphy=9027887&hvtargid=pla-638906394402&psc=1&mcid=df8a82d513d937b38ac19209b20d38be&gclid=Cj0KCQiA3uGqBhDdARIsAFeJ5r2Bf3Hn9BAFTkkVJRDWo13Jtzo2joT1CvOYTTWmDM07E5Ru6yNsvNMaAuECEALw_wcB)
An LED ($0.10) and a resistor ($0.02) makes an EXCELLENT logic level indicator.
A wire jumper and a resistor on the breadboard can be used as a switch.
Two bent wires and a resistor can be used as a momentary switch.
And all the documentation in the world is available on the internet, FOR FREE. Boy, how I wish I had that 50 years ago.
ETC!
You can easily get started for under 35 USD. You can also spend $50,000 and wind up so confused that you never figure it out.
Save your money until you KNOW for CERTAIN what you need and WHY you need it. And buy one or more of the "Cookbooks" that I suggested above. They really are great.
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Yes that's a good point. If the output has to drive any kind of transmission line (or pseudo trans line) then some extra care is necessary.
The effect of a series resistor on the circuit performance may or not be significant. For a line operated logic circuit (like 50 or 60Hz) it probably won't make much difference.
Er no.
If you violate the signal integrity requirements for a clock driving flip flops, then you are just as screwed at 1Hz as at 1GHz. Ditto violating the data's hold time.
Repeat after me: period is irrelevant, transition time is the only significant parameter :)
Hi,
Repeat after me
No thanks.
Of course flip flops have extra specifications, but for gates even some jitter may not matter at very low frequency.
In that case you should not even be using a resistor, or accepting an input from a long line.
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I love the way this "beginners" board launches into the "need" for $10,000, $25,000, or $100,000 worth of test equipment.
That's a hallucination.
I have designed, built, and placed in daily service in commercial facilities, circuits that were based on discrete logic chips using switches, resistors, and analog VOMs for my design lab equipment. It can be done with $25 worth of equipment, for Pete's sake.
Where time is money and/or cost of recalls/service are significant, that can be a false economy.
OTOH, if equipment cannot be made available, it is pleasing to be able to "do more with less".
I still don't have even $2000 worth of equipment but would not hesitate to start on almost any design you can imagine at the beginner or intermediate level. Or even 90% of designs at the advanced level.
One of these types of breadboards is nice to have. They come in many styles and sizes and prices: this is only one example.
https://www.amazon.com/BB400-Solderless-Plug-BreadBoard-tie-points/dp/B0040Z1ERO/ref=asc_df_B0040Z1ERO/?tag=hyprod-20&linkCode=df0&hvadid=241888066999&hvpos=&hvnetw=g&hvrand=3481730356964540888&hvpone=&hvptwo=&hvqmt=&hvdev=c&hvdvcmdl=&hvlocint=&hvlocphy=9027887&hvtargid=pla-638906394402&psc=1&mcid=df8a82d513d937b38ac19209b20d38be&gclid=Cj0KCQiA3uGqBhDdARIsAFeJ5r2Bf3Hn9BAFTkkVJRDWo13Jtzo2joT1CvOYTTWmDM07E5Ru6yNsvNMaAuECEALw_wcB (https://www.amazon.com/BB400-Solderless-Plug-BreadBoard-tie-points/dp/B0040Z1ERO/ref=asc_df_B0040Z1ERO/?tag=hyprod-20&linkCode=df0&hvadid=241888066999&hvpos=&hvnetw=g&hvrand=3481730356964540888&hvpone=&hvptwo=&hvqmt=&hvdev=c&hvdvcmdl=&hvlocint=&hvlocphy=9027887&hvtargid=pla-638906394402&psc=1&mcid=df8a82d513d937b38ac19209b20d38be&gclid=Cj0KCQiA3uGqBhDdARIsAFeJ5r2Bf3Hn9BAFTkkVJRDWo13Jtzo2joT1CvOYTTWmDM07E5Ru6yNsvNMaAuECEALw_wcB)
No, they aren't. All too often they lead to beginners becoming discouraged by inexplicable (to them) behaviour. There are better alternatives.
OTOH an experienced person with a thorough understanding of their limitations can get them to work.
An LED ($0.10) and a resistor ($0.02) makes an EXCELLENT logic level indicator.
A wire jumper and a resistor on the breadboard can be used as a switch.
Two bent wires and a resistor can be used as a momentary switch.
Yes indeed. See my .sig
I used switches, LEDs and a multimeter when I designed and built a 6800 computer from scratch (think Altair 8080).
I did use the university's scope to check the critical non-TTL levels for the 6800 clock, and found overshoot sufficient to have cost me a week's wages (i.e. the price of the 6800). That taught me about stray inductance, probing technique, and the consequences of long wires.
Overall the thing was messy, but it worked well and I learned a lot.
And all the documentation in the world is available on the internet, FOR FREE. Boy, how I wish I had that 50 years ago.
You can easily get started for under 35 USD. You can also spend $50,000 and wind up so confused that you never figure it out.
Save your money until you KNOW for CERTAIN what you need and WHY you need it. And buy one or more of the "Cookbooks" that I suggested above. They really are great.
Mostly very true. But note that the tools which used to cost a year's salary (e.g. a Tek 465, or microprocessor development systems) are now available for small change.
Tools have a significant learning curve. Instantly resorting to complex and expensive tools is not a good foundation for a career. I like to ask people what oscilloscope they would use when designing and implementing the world's fastest scope.
The important point is to think, to understand the strengths and weaknesses of tools and techniques, and to employ the best combination for the task at hand.
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Yes that's a good point. If the output has to drive any kind of transmission line (or pseudo trans line) then some extra care is necessary.
The effect of a series resistor on the circuit performance may or not be significant. For a line operated logic circuit (like 50 or 60Hz) it probably won't make much difference.
Er no.
If you violate the signal integrity requirements for a clock driving flip flops, then you are just as screwed at 1Hz as at 1GHz. Ditto violating the data's hold time.
Repeat after me: period is irrelevant, transition time is the only significant parameter :)
Hi,
Repeat after me
No thanks.
Of course flip flops have extra specifications, but for gates even some jitter may not matter at very low frequency.
In that case you should not even be using a resistor, or accepting an input from a long line.
No.
Timing specifications such as tsu and th are only "extra" in the sense that Vcc voltage specifications are "extra". Violate any of those and behaviour is undefined[1].
With a "long line" a source series resistor is required. Of course that requires that you understand what "long" means, and that the line is a transmission line.
[1] yes, I do know that 1.5-5V 74LVC can work at 0.8V. Just about, with the right room temperature, on a good day, and for a loose definition of "work" :)
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I'll stick with FPGAs...
The advantage of the 74ls74a over FPGA is that they pre-programmed at the factory.
;-)
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I used switches, LEDs and a multimeter when I designed and built a 6800 computer from scratch (think Altair 8080).
Same here, but Z80 and run CP/M with floppy disk. The multimeter was analog with moving needle and I etched the PCB myself.
These days I use a digital oscilloscope, logic analyzer, hardware debugger, and the JLCPCB PCB service. They are so affordable these days.
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I used switches, LEDs and a multimeter when I designed and built a 6800 computer from scratch (think Altair 8080).
Same here, but Z80 and run CP/M with floppy disk. The multimeter was analog with moving needle and I etched the PCB myself.
These days I use a digital oscilloscope, logic analyzer, hardware debugger, and the JLCPCB PCB service. They are so affordable these days.
Ditto!
Except floppies? Luxury! My computer had 128bytes of RAM. That was sufficient to demonstrate principle :)
I still have that MC6810 RAM and the 6800.
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Yes that's a good point. If the output has to drive any kind of transmission line (or pseudo trans line) then some extra care is necessary.
The effect of a series resistor on the circuit performance may or not be significant. For a line operated logic circuit (like 50 or 60Hz) it probably won't make much difference.
Er no.
If you violate the signal integrity requirements for a clock driving flip flops, then you are just as screwed at 1Hz as at 1GHz. Ditto violating the data's hold time.
Repeat after me: period is irrelevant, transition time is the only significant parameter :)
Hi,
Repeat after me
No thanks.
Of course flip flops have extra specifications, but for gates even some jitter may not matter at very low frequency.
In that case you should not even be using a resistor, or accepting an input from a long line.
No.
Timing specifications such as tsu and th are only "extra" in the sense that Vcc voltage specifications are "extra". Violate any of those and behaviour is undefined[1].
With a "long line" a source series resistor is required. Of course that requires that you understand what "long" means, and that the line is a transmission line.
[1] yes, I do know that 1.5-5V 74LVC can work at 0.8V. Just about, with the right room temperature, on a good day, and for a loose definition of "work" :)
I see you really really like the word "No".
This time it does not seem to make any sense though. Maybe you could elaborate a little more.
To me, a long line requires a special type of gate made for that.
-
Yes that's a good point. If the output has to drive any kind of transmission line (or pseudo trans line) then some extra care is necessary.
The effect of a series resistor on the circuit performance may or not be significant. For a line operated logic circuit (like 50 or 60Hz) it probably won't make much difference.
Er no.
If you violate the signal integrity requirements for a clock driving flip flops, then you are just as screwed at 1Hz as at 1GHz. Ditto violating the data's hold time.
Repeat after me: period is irrelevant, transition time is the only significant parameter :)
Hi,
Repeat after me
No thanks.
Of course flip flops have extra specifications, but for gates even some jitter may not matter at very low frequency.
In that case you should not even be using a resistor, or accepting an input from a long line.
No.
Timing specifications such as tsu and th are only "extra" in the sense that Vcc voltage specifications are "extra". Violate any of those and behaviour is undefined[1].
With a "long line" a source series resistor is required. Of course that requires that you understand what "long" means, and that the line is a transmission line.
[1] yes, I do know that 1.5-5V 74LVC can work at 0.8V. Just about, with the right room temperature, on a good day, and for a loose definition of "work" :)
I see you really really like the word "No".
This time it does not seem to make any sense though. Maybe you could elaborate a little more.
To me, a long line requires a special type of gate made for that.
I prefer the word "agreed", and use it as appropriate.
I'm not going to (poorly) repeat standard transmission line theory and practice. See pointers earlier in the thread, or use google.
-
Yes that's a good point. If the output has to drive any kind of transmission line (or pseudo trans line) then some extra care is necessary.
The effect of a series resistor on the circuit performance may or not be significant. For a line operated logic circuit (like 50 or 60Hz) it probably won't make much difference.
Er no.
If you violate the signal integrity requirements for a clock driving flip flops, then you are just as screwed at 1Hz as at 1GHz. Ditto violating the data's hold time.
Repeat after me: period is irrelevant, transition time is the only significant parameter :)
Hi,
Repeat after me
No thanks.
Of course flip flops have extra specifications, but for gates even some jitter may not matter at very low frequency.
In that case you should not even be using a resistor, or accepting an input from a long line.
No.
Timing specifications such as tsu and th are only "extra" in the sense that Vcc voltage specifications are "extra". Violate any of those and behaviour is undefined[1].
With a "long line" a source series resistor is required. Of course that requires that you understand what "long" means, and that the line is a transmission line.
[1] yes, I do know that 1.5-5V 74LVC can work at 0.8V. Just about, with the right room temperature, on a good day, and for a loose definition of "work" :)
I see you really really like the word "No".
This time it does not seem to make any sense though. Maybe you could elaborate a little more.
To me, a long line requires a special type of gate made for that.
I prefer the word "agreed", and use it as appropriate.
I'm not going to (poorly) repeat standard transmission line theory and practice. See pointers earlier in the thread, or use google.
Hi,
I will if you will :)
-
Yes that's a good point. If the output has to drive any kind of transmission line (or pseudo trans line) then some extra care is necessary.
The effect of a series resistor on the circuit performance may or not be significant. For a line operated logic circuit (like 50 or 60Hz) it probably won't make much difference.
Er no.
If you violate the signal integrity requirements for a clock driving flip flops, then you are just as screwed at 1Hz as at 1GHz. Ditto violating the data's hold time.
Repeat after me: period is irrelevant, transition time is the only significant parameter :)
Hi,
Repeat after me
No thanks.
Of course flip flops have extra specifications, but for gates even some jitter may not matter at very low frequency.
In that case you should not even be using a resistor, or accepting an input from a long line.
No.
Timing specifications such as tsu and th are only "extra" in the sense that Vcc voltage specifications are "extra". Violate any of those and behaviour is undefined[1].
With a "long line" a source series resistor is required. Of course that requires that you understand what "long" means, and that the line is a transmission line.
[1] yes, I do know that 1.5-5V 74LVC can work at 0.8V. Just about, with the right room temperature, on a good day, and for a loose definition of "work" :)
I see you really really like the word "No".
This time it does not seem to make any sense though. Maybe you could elaborate a little more.
To me, a long line requires a special type of gate made for that.
I prefer the word "agreed", and use it as appropriate.
I'm not going to (poorly) repeat standard transmission line theory and practice. See pointers earlier in the thread, or use google.
Hi,
I will if you will :)
Que? What do you mean by that?
Or are you just here for a 5 minute argument?