MOSFT capacitance

[stafil]

Hi!

In the circuit below I understand that the undershoot/overshoot and slow rise time I see is because of the MOSFET capacitance, but I have a couple of questions.

1. Which capacitance specifically is it? Is it the Drain-Gate capacitance that causes this?

2. Any way to fix all of the above, rise time and understhoot/overshoot, assuming I don't have any control over the R1(20k) Resistor and and V2(5V) voltage source?

(The greenish line is the voltage at the drain, and the blueish(turquoise) the voltage at the gate)

Thanks,
Stavros

[Manul]

I will try to put it simple.

Slow rise is because:

1. When gate voltage goes down, drain is at almost 0 volts
2. There is capacitance between drain and source Cds
3. Cds charges up from V2 through R1
4. Rise time is determined by Cds and R1 time constant

You cannot do much about it without changing R1, or Cds (mosfet used).

Undershoot and overshoot is because:

1. There is capacitance between gate and drain Cgd
2. Extremely fast gate voltage rise and fall times means that it includes very high frequencies
3. For these high frequencies Cgd has low impedance and becomes significant path
4. So it pulls down and up drain voltage, while Cgd charges/discharges

To solve undershoot/overshoot you need to slow down gate rise and fall times by adding current limiting gate resistor. Together with gate source capacitance it creates low pass filter. It also helps to stop gate ringing. Almost a must in all practical circuits.

[stafil]

I will try to put it simple.

Slow rise is because:

1. When gate voltage goes down, drain is at almost 0 volts
2. There is capacitance between drain and source Cds
3. Cds charges up from V2 through R1
4. Rise time is determined by Cds and R1 time constant, you cannot do much about it without changing R1

Undershoot and overshoot is because:

1. There is capacitance between gate and drain Cgd
2. Extremely fast gate voltage rise and fall times means that it includes very high frequencies
3. For these high frequencies Cgd has low impedance and becomes significant path
4. So it pulls down and up drain voltage, while Cgd charges/discharges

To solve undershoot/overshoot you need to slow down gate rise and fall times by adding current limiting gate resistor. Together with gate source capacitance it creates low pass filter. It also helps to stop gate ringing. Almost a must in all practical circuits.

Thanks. I wish all the answers to all the questions I ever had were so precise and well explained!

[Manul]

As a side note - in practice you have gate resistor even if there is none. By that I mean, that the gate driving source has some internal resistance. For example - arduino output pin can have 30-50 ohms of internal resistance. Also mosfet gate itself has some little resistance. In a simulation it is different story. It may simulate gate resistance, but signal source is by default 0 ohms.

Also real circuits have inductances everywhere. Then it really starts to get messy.

[Zero999]

Power MOSFETs aren't designed to be used in this manner. It's possible to get MOSFETs with a smaller drain-source capacitance such as the FDV301N.
https://www.onsemi.com/pub/Collateral/FDV301N-D.PDF

Another option is to use a logic gate with an open grain output, such as the 74LVC1G06.
http://www.ti.com/lit/ds/symlink/sn74lvc1g06.pdf