Author Topic: Clamping Split Rail Node to GND using Transistor(s)  (Read 3085 times)

0 Members and 1 Guest are viewing this topic.

Offline MechatrommerTopic starter

  • Super Contributor
  • ***
  • Posts: 11714
  • Country: my
  • reassessing directives...
Clamping Split Rail Node to GND using Transistor(s)
« on: August 01, 2019, 01:01:46 pm »
hi i have this circuit (attached). at some point in time during operation when capacitors build up charges, i want to reset or "clamp" the red arrowed node to GND (0V) for a moment using transistor solution, and then release the reset condition again so it will work normally again. if anyone wonder, this is part of opamp PID circuit, and shown is the Integral part of it, the reset is to avoid Integral windup if i'm not mistaken, it is the place to do the windup reset. please tell me if i'm wrong.

if it +ve voltage only, it will be easy with just a single NPN shorted to ground when base is HI (and release clamp when LO). but this is split rails, can be +ve and -ve voltage. if i put relay to it, it will work the way i want, but this is high repetition (frequency) rate, mechanical relay wont keep up and will die in no time i suspect. i have switch IC including bidirectional type on a board that i can reuse, but i think thats specialty component probably add price to my circuit, and complexity to provide additional logic power rail. i will use it if no other better and simpler discrete transistor solution that can take up say ±15V voltage swing. so can anyone suggest the simplest transistors solution for this? thanks.

« Last Edit: August 02, 2019, 12:11:39 am by Mechatrommer »
Nature: Evolution and the Illusion of Randomness (Stephen L. Talbott): Its now indisputable that... organisms “expertise” contextualizes its genome, and its nonsense to say that these powers are under the control of the genome being contextualized - Barbara McClintock
 

Online Ian.M

  • Super Contributor
  • ***
  • Posts: 13217
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #1 on: August 01, 2019, 02:31:16 pm »
To reset the integrator you need to discharge Cintg.   Grounding I- wont do that as with I+ and I- at the same voltage, the output will try to go to Open_Loop_Gain*Input_Offset_Voltage, which will probably rail it.   Therefore you need to short Cintg, i.e connect I- to Out.

The easiest way to do that without complex level shifting or drive circuits would be a PhotoMOS optocoupler + just enough series resistance to prevent the optocoupler's peak load current being exceeded when there's a full 15V+Vstg1 on the cap.

You could use an analog switch, but handling the worst case +/-15V, + providing it with a logic supply+ level shifting its control signal may be more complex that you care to implement, and also its unlikely to have anywhere near the current handling capability of a PhotoMOS optocoupler, so resets will be slower with a higher residual error.

Discrete MOSFETs would be complex to use due to Vgs max limits + the need to use either four terminal devices with a separate substrate pin or back to back pairs.  If you don't need to hold the clamped reset state, its possible you could use a pair of back to back (source to source) MOSFETs with a pulse transformer for gate drive, however a transformer that can handle a long enough reset pulse without saturating isn't going to be small or cheap.  If you need DC clamping, you need two pairs of back to back MOSFETS, one pair N channel and the other P channel so you can guarantee at least one pair is on when you take their gates to opposite rails.  You also need Zener clamping for the gates and a rather complex drive circuit to avoid injecting any current into In- when not resetting.

Symmetrical transistors with an adequate Vebo breakdown voltage to handle the worst case voltage accross the capacitor are rare like hens teeth nowadays.  Without them a BJT solution will be over-complex with a whole mess of steering diodes, which would also increase the residual offset.  The few remaining available transistors designed for reversable operation (e.g. 2SC2878 or 2SC3326) typically don't have high enough Vceo ratings for your application.  It would be a different  matter if you were using +/-5V or +/-9V rails for your OPAMP.
« Last Edit: August 01, 2019, 02:35:34 pm by Ian.M »
 
The following users thanked this post: Mechatrommer

Offline MechatrommerTopic starter

  • Super Contributor
  • ***
  • Posts: 11714
  • Country: my
  • reassessing directives...
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #2 on: August 01, 2019, 04:27:46 pm »
thanks Ian. you are right i missed the point that opamp output will go to rail if i simply short its -ve input, i thought it simply go to 0V and discharge the capacitors. looking at digikey, photoFET optocoupler such as H11F1M is $4, quite luxurious for the circuit i'm building. coincidentally i'm waiting parts from digikey to arrive soon, among them is MOC3041 triac optocoupler as replacement damaged part of my soldering station 852AD, i bought 10 pcs so i will have extra parts to keep, less than $1 each. although it has 1.5V forward voltage, i think it can provide "limited" bidirectional reset to short capacitance, correct? your later suggestions and explanations seem to result in circuit complication...

btw, i deviced the discrete transistors bidirectional clamp to GND in spice just few minutes after making this thread (attached) but since grounding the opamp -ve input is a bad idea, so its going to trash... 4 bjt's and few resistors, it looks like even if i can cramp them in smallest space, they will be no smaller than the DIP8 footprint let alone DIP6 of the MOC3041. luckily its also pin compatible with H11F1M fet, so in case later i can justify buying the $4 part, i can simply put it in there without making new pcb. i think i am making sense here ;D no? thanks Ian for the optocoupler idea.
« Last Edit: August 02, 2019, 12:10:38 am by Mechatrommer »
Nature: Evolution and the Illusion of Randomness (Stephen L. Talbott): Its now indisputable that... organisms “expertise” contextualizes its genome, and its nonsense to say that these powers are under the control of the genome being contextualized - Barbara McClintock
 

Offline David Hess

  • Super Contributor
  • ***
  • Posts: 17428
  • Country: us
  • DavidH
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #3 on: August 01, 2019, 09:38:36 pm »
Like Ian.M says, you have to clamp across the capacitor for the reasons he gave.

In the past a JFET might be used and that is still a good solution.  Before they existed, someone probably did it with a current driven diode bridge.  Photo resistors have also been used.  Ian.M's suggestion of a photoFET or photoMOS optocoupler is one of the simplest ways.

Another way which is sometimes used is to have a second operational amplifier drive a current into the inverting input until the output reaches ground.
 
The following users thanked this post: Mechatrommer

Online Ian.M

  • Super Contributor
  • ***
  • Posts: 13217
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #4 on: August 01, 2019, 10:32:48 pm »
Here's a way of doing it with a pair of back to back N-MOSFETs.   The trick is to bias the sources to the negative rail to guarantee you can initially apply enough gate drive to turn them on.  Once it starts to reset, there's no problem maintaining the gate drive. However the bias must be disconnected at the end of the reset pulse + the gate voltage needs to be held up with a capacitor to the joined sources with a resistor across it to control the rate of turnoff to avoid excessive charge injection at turnoff.  The drive circuit is therefore quite complex, verging on fugly.

AAGH!  |O The attachment went AWOL.  :palm:
« Last Edit: August 01, 2019, 11:05:55 pm by Ian.M »
 
The following users thanked this post: Mechatrommer, mikerj

Offline Brutte

  • Frequent Contributor
  • **
  • Posts: 614
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #5 on: August 01, 2019, 10:49:37 pm »
Why do you use two polarized capacitors back-to-back in the feedback loop?
 

Offline David Hess

  • Super Contributor
  • ***
  • Posts: 17428
  • Country: us
  • DavidH
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #6 on: August 01, 2019, 10:56:04 pm »
Oh, back to back MOSFETs reminds me that a 4 pin MOSFET where the substrate is a separate pin can also be used.  4 pin MOSFETs have poor availability but Linear Systems still makes them.
 

Online Ian.M

  • Super Contributor
  • ***
  • Posts: 13217
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #7 on: August 01, 2019, 11:13:42 pm »
If the gate oxide is only rated for +/-20V with respect to the channel, I think you are going to have trouble driving the four terminal MOSFET gate safely if the rails are +/-15V.   Worst case, with the integrator output railed and its input fully at the opposite rail, there will be nearly 30V across the capacitor, and you then have the problem of clamping the gate with respect to the more negative channel terminal (assuming NMOS).  As I said earlier, it gets a lot easier with +/-9V or less rails for the OPAMP.
 

Offline MechatrommerTopic starter

  • Super Contributor
  • ***
  • Posts: 11714
  • Country: my
  • reassessing directives...
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #8 on: August 01, 2019, 11:47:05 pm »
@David, thanks! your opamp solution is another way of doing it, thats feasible in my circuit! Ian, thanks for your effort making the circuit in LTSpice i appreciate it. it requires more components 6 transistors/fet, diodes etc, it will increase board size. with simpler opto and secondary opamp solution, i trust your fet back to back solution can be usefull in another application. will be a good reference.

Why do you use two polarized capacitors back-to-back in the feedback loop?
i got it from a reference in the net. when looking at it, its using 470uF capacitors so i guess that big capacitance is not available in ceramics or tantalum format? so in order to get non polarized capacitor, 2 back to back polarized electrolytics are used.

https://www.nutsvolts.com/magazine/article/the_pid_controller_part_1

« Last Edit: August 02, 2019, 12:23:38 am by Mechatrommer »
Nature: Evolution and the Illusion of Randomness (Stephen L. Talbott): Its now indisputable that... organisms “expertise” contextualizes its genome, and its nonsense to say that these powers are under the control of the genome being contextualized - Barbara McClintock
 

Offline MechatrommerTopic starter

  • Super Contributor
  • ***
  • Posts: 11714
  • Country: my
  • reassessing directives...
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #9 on: August 02, 2019, 12:09:11 am »
the opto solution to this (attached)... currently trying the secondary opamp solution as the opto pins hit some of other components on the pcb, trying to make as less space as possible, allocated pcb area is only 2x6cm with 3 smd opamp ic on the board (8 opamps) + auxs resistors etc, and i still have one extra opamp that can be used as integrator reset circuit.
Nature: Evolution and the Illusion of Randomness (Stephen L. Talbott): Its now indisputable that... organisms “expertise” contextualizes its genome, and its nonsense to say that these powers are under the control of the genome being contextualized - Barbara McClintock
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #10 on: August 02, 2019, 01:02:19 am »
Is it supposed to be reset to zero during the event, or held still?

In either case you most definitely do not want to yank on the virtual ground.  Consider what that equivalent circuit actually is: you're connecting a very low resistance to that pin, along with some nonzero offset voltage (which may be the amp's Vos itself, or built-in offsets in the switch or surrounding circuit).  In other words, you've added a second input, with a series resistance MASSIVELY smaller than the normal input.  It'll go bonkers.

What you need to do, is shunt the output to the input, discharging the capacitors; or, for a hold function, disconnecting the normal input so it's an amp with a capacitor wrapped around it, just sitting there.

Both are easily done with normal CMOS switches (I would recommend adding an external resistor to limit the power dissipation from all that capacitance). :)

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
The following users thanked this post: Mechatrommer

Offline MechatrommerTopic starter

  • Super Contributor
  • ***
  • Posts: 11714
  • Country: my
  • reassessing directives...
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #11 on: August 02, 2019, 02:09:22 am »
Is it supposed to be reset to zero during the event, or held still?
the idea is to discharge capacitors Cintg* whenever reset is required, the reset control is by toggling the RST_Intgr digital control pin (see pink colored attached) to HI. so the ideal condition during reset state is 0V on all U2A's IO pins or very close to that esp on U2A's -ve input, so to keep capacitors charges minimal (to avoid worse Integral windup). this switch must be able to be released for the integrator opamp to work normally again as if its not connected to any reset/clamp circuitry.

In either case you most definitely do not want to yank on the virtual ground.  Consider what that equivalent circuit actually is: you're connecting a very low resistance to that pin, along with some nonzero offset voltage (which may be the amp's Vos itself, or built-in offsets in the switch or surrounding circuit).  In other words, you've added a second input, with a series resistance MASSIVELY smaller than the normal input.  It'll go bonkers.
thats why HI impedance circuit during OFF state is required, during reset (ON) state, the impedance should be lowest to be able to discharge capacitors quickly. and to add insult to the injury, this is dual rail system where current can flow in both direction.

What you need to do, is shunt the output to the input, discharging the capacitors; or, for a hold function, disconnecting the normal input so it's an amp with a capacitor wrapped around it, just sitting there.
Both are easily done with normal CMOS switches (I would recommend adding an external resistor to limit the power dissipation from all that capacitance). :)
that is what Ian suggested and i think i will implement it in the circuit using triac opto that is currently coming my way. thanks for your suggestion on the CMOS switch.

coupled with David's idea of secondary opamp, i think i've made the "active" version of triac to deal with 1.5V forward voltage drop, so i guess with circuit below, the Vdrop should be eliminated and make an ideal reset circuit, no need $4 H11F1M PhotoFET, correct? (R7 is current limiter, i think i can use 0R short if U3B can withstand a short such as the TL072/074, for other opamp that cannot be shorted, R7 will be there)  :-+
« Last Edit: August 02, 2019, 02:24:52 am by Mechatrommer »
Nature: Evolution and the Illusion of Randomness (Stephen L. Talbott): Its now indisputable that... organisms “expertise” contextualizes its genome, and its nonsense to say that these powers are under the control of the genome being contextualized - Barbara McClintock
 

Online Zero999

  • Super Contributor
  • ***
  • Posts: 20363
  • Country: gb
  • 0999
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #12 on: August 02, 2019, 09:46:53 am »
Why not use an analogue switch IC?

DG468 single channel
https://www.vishay.com/docs/74413/dg467.pdf

DG445 four channel
https://docs-emea.rs-online.com/webdocs/1300/0900766b813009f9.pdf
 
The following users thanked this post: Mechatrommer

Offline MechatrommerTopic starter

  • Super Contributor
  • ***
  • Posts: 11714
  • Country: my
  • reassessing directives...
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #13 on: August 02, 2019, 12:32:10 pm »
Why not use an analogue switch IC?

DG468 single channel
https://www.vishay.com/docs/74413/dg467.pdf

DG445 four channel
https://docs-emea.rs-online.com/webdocs/1300/0900766b813009f9.pdf
thanks for the suggestion Hero, it helps me on part searching and selection time several order of magnitude. i've put few DG468 into my digikey cart...undoubtedly this part is the simplest i can get. my only concern now is maximum current and how quickly they can discharge the ~220uF capacitance, including the MOC3041 (30mA cont, 1A surge capability). btw, the MOC3041 arrived today i can proceed repairing my 852AD station and ready to be used on circuit... but the pcb i will send to fab house soon, so it will take another weeks to arrive. thinking about it, before i send the pcb, i will implement analog switch as well on the pcb along with the triac opto solution, so i can switch between them to see which works better. analog switch has size and component count advantage, so if triac opto does not show significant improvement, maybe analog switch is the solution in the next revision. this can be part of my learning process.
« Last Edit: August 02, 2019, 12:41:50 pm by Mechatrommer »
Nature: Evolution and the Illusion of Randomness (Stephen L. Talbott): Its now indisputable that... organisms “expertise” contextualizes its genome, and its nonsense to say that these powers are under the control of the genome being contextualized - Barbara McClintock
 

Online Zero999

  • Super Contributor
  • ***
  • Posts: 20363
  • Country: gb
  • 0999
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #14 on: August 02, 2019, 01:02:08 pm »
In theory the capacitor never fully discharges, irrespective of which method you choose.

Analogue switches have an on resistance, forming an RC circuit with the capacitor. The DG468 has a on resistance of 10R, so the time constant will be 2.2ms, with a 220µF capacitor.

A TRIAC will stop conducting once the current falls below a certain level, so will always leave some charge left in the capacitor. The MOC3041 is a bad choice, because it has a zero crossing unit which prevents it from triggering at low voltages, although it might work in this case because the voltage across the capacitor will always be below 12V.

Lastly your circuit doesn't close the loop at DC. There's no negative feedback between the non-inverting input and output. In practise you might get away with it with the TL072, which has such tiny bias currents and a high input impedance, the leakage in the capacitor and switch might be enough.

 
The following users thanked this post: Mechatrommer

Online Ian.M

  • Super Contributor
  • ***
  • Posts: 13217
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #15 on: August 02, 2019, 01:09:49 pm »
Why not use an analogue switch IC?

DG468 single channel
https://www.vishay.com/docs/74413/dg467.pdf

DG445 four channel
https://docs-emea.rs-online.com/webdocs/1300/0900766b813009f9.pdf
An excellent suggestion, which would work well with a smaller integration capacitor, however Mechatrommer's got very large integration capacitor and the analog switches you suggested are only good for max 30mA, (100mA 1ms pulse), so for the DG468 you'd need a 1K
series discharge resistor to keep it safe, which with a 235uF integration capacitor (2x 470uF back to back) and +/-15V rails, gives a worst case time to discharge of well over one second.  Use a DG445, and it can do 30mA per channel - parallel them all each with its own series 1K resistor and it will handle 120mA, which lets you get the reset time down to around 0.28 seconds (to 1% of initial voltage).

That's still pretty poor compared to my back-to-back MOSFETs, as the BSH114 MOSFETs I selected can handle 3.4A peak for long enough to be useful, and around 0.75A continuous (derated to 50 deg C), which lets you reset the integrator an order of magnitude faster.

The H11F1M PhotoFET optocoupler Mechatrommer briefly considered is also unsuitable for resetting such a large capacitor - its nominally good for 100mA abs. max. but its output characteristic (fig. 2) shows it will be unlikely to pass  more than a few mA. A TLP175A PhotoMOS relay would be more suitable as that can actually deliver its 100mA rated load current.

... thinking about it, before i send the pcb, i will implement analog switch as well on the pcb along with the triac opto solution, so i can switch between them to see which works better. analog switch has size and component count advantage, so if triac opto does not show significant improvement, maybe analog switch is the solution in the next revision. this can be part of my learning process.
I think your OptoTRIAC idea is going to disappoint you.  The OPAMP you are using to cancel its On state voltage drop wont be able to supply enough current for a fast reset, and as Zero999 just pointed out, a MOC3041 has a zero crossing detector so you cant even trigger it with a significant steady DC bias voltage across it. (I disagree with Zero999: worst case, full windup railing the output plus continued input at the opposite rail you could have over 25V across the integrator cap, 30V if the OPAMPs have rail-to-rail outputs.)

A MOC301xM or MOC302xM series OptoTRIAC, without a zero crossing detector would work as a coarse integrator reset. I wouldn't recommend trying to cancel its on state voltage with an open-loop OPAMP as you are likely to run into problems with failure to commutate due to excess dV/dt, unless you limit the OPAMP slew rate + you'll still need a beefy push/pull booster stage after the OPAMP.  A better idea would be to pair it in parallel with one of Zero999's suggested analog switches -  Fire the OptoTRIAC first to get it 95% of the way to reset and to handle the high current, then use the analog switch to discharge the last few volts. 
« Last Edit: August 02, 2019, 01:15:30 pm by Ian.M »
 
The following users thanked this post: Mechatrommer

Online Ian.M

  • Super Contributor
  • ***
  • Posts: 13217
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #16 on: August 02, 2019, 01:30:26 pm »
An alternative idea that may be worth looking at for a *really* beefy integrator reset would be a small isolated DC-DC converter, switched on its input side, providing gate drive to a pair of back to back N-MOSFETs (with respect to their commoned sources).  It will need a discharge resistor as well and will be rather slow compared to a PhotoMOS relay, but may be cost-competitive compared to a PhotoMOS with a high peak current rating.    As the DC-DC converter only runs during the reset pulse, its EMI shouldn't be an issue for the rest of the circuit.
« Last Edit: August 02, 2019, 01:33:28 pm by Ian.M »
 
The following users thanked this post: Mechatrommer

Online Zero999

  • Super Contributor
  • ***
  • Posts: 20363
  • Country: gb
  • 0999
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #17 on: August 02, 2019, 02:51:07 pm »
I agree  the 235µF capacitor charged to 30V would no doubt zap the analogue switch. The solution is to make the integration capacitor much smaller. There's no point in over-engineering the reset circuitry, when using a much smaller capacitor and higher value timing resistor would be much easier.

Unfortunately, the DG468 doesn't specify how much of a capacitive discharge it can withstand. Do you think 2.2µF would be OK? I think a 1k discharge resistor is a bit too conservative. It can withstand 100mA peak and will still be able to take more than 30mA, at a low duty.
« Last Edit: August 02, 2019, 04:14:28 pm by Zero999 »
 

Offline MechatrommerTopic starter

  • Super Contributor
  • ***
  • Posts: 11714
  • Country: my
  • reassessing directives...
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #18 on: August 02, 2019, 04:32:27 pm »
That's still pretty poor compared to my back-to-back MOSFETs
still figuring out your circuit. i think i understand the shorting current will shot through body diode of one of the mosfet to the other capacitor's pin, correct? and the rest is i think as you said, source biasing etc. unfortunately i have no more room space to put all the components, let the opto and analog switch go first (i stacked them one on top the other because only one will be populated at a time, and i dont have much space other than about the DIP8 footprint size. i will learn their behaviour, i'll try to understand how they work (learn the hard way) if they indeed dissapointing, i will make add-on pcb to populate your circuit in the next spin. i think if i have 2x2cm board size will be enough. the pcb is ready to go maybe tomorrow or the next monday.

otoh, buying DG468 switch will not hurt as i always wanted this type of part for another project. the MOC3041 bought because i need to repair my stuff using it, and also extra part to keep handy for other project, its not so expensive. i think i already have all the parts to build your circuit, i have 6A nmosfet AO3400 for that, zeners bjt etc, but the space to populate them is currently unavailable.

The solution is to make the integration capacitor much smaller. There's no point in over-engineering the reset circuitry, when using a much smaller capacitor and higher value timing resistor would be much easier.
the capacitance value will be decided during PID tuning, different motor will use different integrator value, i cannot choose whatever value. the values shown are only copied from the circuit i follow in the above link. if the system i will be driving requires less capacitance and smaller power rails, then maybe analog switch will be just fine, but bigger integrator system maybe need Ian's circuit. so it depends, i cannot give the answer right now..
Nature: Evolution and the Illusion of Randomness (Stephen L. Talbott): Its now indisputable that... organisms “expertise” contextualizes its genome, and its nonsense to say that these powers are under the control of the genome being contextualized - Barbara McClintock
 

Online Zero999

  • Super Contributor
  • ***
  • Posts: 20363
  • Country: gb
  • 0999
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #19 on: August 02, 2019, 04:47:07 pm »
The solution is to make the integration capacitor much smaller. There's no point in over-engineering the reset circuitry, when using a much smaller capacitor and higher value timing resistor would be much easier.
the capacitance value will be decided during PID tuning, different motor will use different integrator value, i cannot choose whatever value. the values shown are only copied from the circuit i follow in the above link. if the system i will be driving requires less capacitance and smaller power rails, then maybe analog switch will be just fine, but bigger integrator system maybe need Ian's circuit. so it depends, i cannot give the answer right now..
Oh, I do understand that, but the integration time constant is proportional to the RC time constant, so if you change 470µF for 47µF and the resistor from 100k to 1M, then it should work the same.

How about using a small relay? There are plenty of tiny relays available which should fit the bill.
https://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf
https://docs-emea.rs-online.com/webdocs/1398/0900766b81398222.pdf
 

Offline MechatrommerTopic starter

  • Super Contributor
  • ***
  • Posts: 11714
  • Country: my
  • reassessing directives...
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #20 on: August 02, 2019, 06:11:50 pm »
Oh, I do understand that, but the integration time constant is proportional to the RC time constant, so if you change 470µF for 47µF and the resistor from 100k to 1M, then it should work the same.
oh ok, maybe thats possible. when pcb completed, i will try biggest R in order to reduce C as much as possible.

How about using a small relay? There are plenty of tiny relays available which should fit the bill.
https://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf
https://docs-emea.rs-online.com/webdocs/1398/0900766b81398222.pdf
yes as stated in OP, mechanical relay can be used but only very low switching frequency, maybe 1Hz and below will be workable. i have mini relays in stock omron G5V, if i need it i can make bodged connection to pcb later. thanks for the suggestion..
Nature: Evolution and the Illusion of Randomness (Stephen L. Talbott): Its now indisputable that... organisms “expertise” contextualizes its genome, and its nonsense to say that these powers are under the control of the genome being contextualized - Barbara McClintock
 

Online Ian.M

  • Super Contributor
  • ***
  • Posts: 13217
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #21 on: August 02, 2019, 08:19:07 pm »
That's still pretty poor compared to my back-to-back MOSFETs
still figuring out your circuit. i think i understand the shorting current will shot through body diode of one of the mosfet to the other capacitor's pin, correct? and the rest is i think as you said, source biasing etc.
Not quite.  If the MOSFET on the more positive side has a lower threshold, the negative side MOSFET's body diode may conduct briefly, but as its gate voltage rises, its channel very soon becomes fully enhanced, and conducts in reverse, bypassing the body diode.  If  the thresholds are the other way round, the negative side MOSFET channel becomes enhanced before its body diode conducts.   Therefore the total voltage drop is only limited by 2*I*Rds_on  so it can nearly fully reset the integrator.  Once the pulse ends so there is no current from the gate drive circuit, the C2+ 2*Cgs, R3 time constant gives extra time with no bias current causing offset voltages to complete resetting the integrator.  It should be noted that ideally the integrator input (to the left of R1) should be at 0V during the reset pulse to minimise the residual offset.
unfortunately i have no more room space to put all the components, let the opto and analog switch go first (i stacked them one on top the other because only one will be populated at a time, and i dont have much space other than about the DIP8 footprint size. i will learn their behaviour, i'll try to understand how they work (learn the hard way) if they indeed dissapointing, i will make add-on pcb to populate your circuit in the next spin. i think if i have 2x2cm board size will be enough. the pcb is ready to go maybe tomorrow or the next monday.
....
 i think i already have all the parts to build your circuit, i have 6A nmosfet AO3400 for that, zeners bjt etc, but the space to populate them is currently unavailable.
Knock it up on protoboard and patch-wire it in for testing.  N.B. if your logic ground is at -15V, you can omit Q1 (short C-E).  If using 3.3V logic, reduce R4 to 4K7 (5K6 if no Q1).
The Zener should be chosen to be around 3/4 of the MOSFETs' Vgs_max. 

otoh, buying DG468 switch will not hurt as i always wanted this type of part for another project. the MOC3041 bought because i need to repair my stuff using it, and also extra part to keep handy for other project, its not so expensive.
The solution is to make the integration capacitor much smaller. There's no point in over-engineering the reset circuitry, when using a much smaller capacitor and higher value timing resistor would be much easier.
the capacitance value will be decided during PID tuning, different motor will use different integrator value, i cannot choose whatever value. the values shown are only copied from the circuit i follow in the above link. if the system i will be driving requires less capacitance and smaller power rails, then maybe analog switch will be just fine, but bigger integrator system maybe need Ian's circuit. so it depends, i cannot give the answer right now..
I think you are premature going to a PCB layout.   More development on solderless breadboard or protoboard would have been helpful.    e.g. 22uF non-polarised electrolytics are readily available so if you follow Zero999's suggestion of trading C for R to maintain the same time constant, you could potentially save quite a bit of board space.  However increasing R makes the integrator proportionately more sensitive to leakage current, so some testing at elevated temperature would be advisable.

A broader overview of the whole problem would be helpful, as it smells like you have an X-Y problem, and unless you have a *HARD* constraint of no MCUs,  software PID, with the MCU PWMing an H-bridge would almost certainly be easier to tune, more compact, and have far lower dissipation.  It also removes the need for an external windup detector and integrator reset pulse generator.
« Last Edit: August 02, 2019, 08:21:55 pm by Ian.M »
 

Online Zero999

  • Super Contributor
  • ***
  • Posts: 20363
  • Country: gb
  • 0999
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #22 on: August 02, 2019, 08:53:11 pm »
Oh, I do understand that, but the integration time constant is proportional to the RC time constant, so if you change 470µF for 47µF and the resistor from 100k to 1M, then it should work the same.
oh ok, maybe thats possible. when pcb completed, i will try biggest R in order to reduce C as much as possible.

How about using a small relay? There are plenty of tiny relays available which should fit the bill.
https://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf
https://docs-emea.rs-online.com/webdocs/1398/0900766b81398222.pdf
yes as stated in OP, mechanical relay can be used but only very low switching frequency, maybe 1Hz and below will be workable. i have mini relays in stock omron G5V, if i need it i can make bodged connection to pcb later. thanks for the suggestion..
I'd even try smaller capacitors and higher value resistors, say 10M and a 2.2μF but as Ian says, there will come a point when leakage becomes significant.

How fast does this need to reset? Sorry, if you've said already. I've quickly flicked through the thread, but don't have time to read it in great detail. Small relays are relatively fast. The ones I linked to all switch on in under 3ms.

I agree with Ian, that going to a PCB at this stage is jumping the gun.
 

Offline MechatrommerTopic starter

  • Super Contributor
  • ***
  • Posts: 11714
  • Country: my
  • reassessing directives...
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #23 on: August 02, 2019, 09:08:06 pm »
I think you are premature going to a PCB layout....
A broader overview of the whole problem would be helpful, as it smells like you have an X-Y problem, and unless you have a *HARD* constraint of no MCUs,  software PID, with the MCU PWMing an H-bridge would almost certainly be easier to tune, more compact, and have far lower dissipation.  It also removes the need for an external windup detector and integrator reset pulse generator.
i'm well aware of soft-pid have done that but not have enough time yet to tune correctly. this time i want to try hard-pid using opamps, mostly for educational purpose, the pcb consists many other small designs, so this pid circuit is only to fill up the free space on the $5 10x10cm pcb. since its cheap, i dont want to mess with protoboard and flying wires anymore, sometime took much longer than on proper pcb, and i usually left the incomplete proto/bread board circuit to the side while doing other stuffs, when i come back few weeks later, i dont remember whats that protoboard is doing, i have to unsolder again to recover the parts/board etc. pcb have labelling that reminds me what it is. anyway, i've sent the pcb to seeedstudio an hour ago, then i made last time modification but i cannot change the file anymore dough, but nevermind just a small change i can cut traces later :-\

How fast does this need to reset?
well as fast as it can be, 10Hz? 1KHz? 100KHz? i dont know but faster is better. i'll see how high the limit of that small pcb module can go, if i need higher performance, i can do rev2 later. as i said, just for educational only to get a picture what application can use this circuit.

btw, i also put jumpers on the pcb to entirely disable I or D or both term, so i tried to make this circuit to be highly configurable to find sweet spot for various systems that i'm going to test.. the board is like a small module with IO and power pins. see attached to get the better picture.
Nature: Evolution and the Illusion of Randomness (Stephen L. Talbott): Its now indisputable that... organisms “expertise” contextualizes its genome, and its nonsense to say that these powers are under the control of the genome being contextualized - Barbara McClintock
 

Online Ian.M

  • Super Contributor
  • ***
  • Posts: 13217
Re: Clamping Split Rail Node to GND using Transistor(s)
« Reply #24 on: August 02, 2019, 11:06:03 pm »
As the aim is self-education, what you probably should have done is design simpler more general purpose analog computing building blocks (e.g. summers, differential amplifiers, integrators, differentiators, multipliers, lin=>log and log=> lin, etc.) to use up the spare PCB space.  Add pin headers and pop them in a solderless breadboard to build your PID controller. When you have something workable, if you want to take it further then's the time to do a final PCB layout.

However that will have to wait for another time.   Do follow up with the PID controller results + details of the motor, its mechanical load, and whatever you are using for a power stage to drive it.
 
The following users thanked this post: Mechatrommer


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf