Clarification on TL494 Circuit – Drive Circuit--- Role of R7, R9, VT1 & VT2

[ommsiva]

Dear all,

I came across the below TL494-based power supply circuit on the web and started analyzing its operation. While going through the schematic, I am facing some difficulty in clearly understanding the design logic behind the selection and connection of R7, R9, and the driver transistors VT1 & VT2. I would appreciate your guidance to validate and correct my understanding.

1. TL494 Output Behavior (Pin

As per my understanding, pin 8 of the TL494 is the collector of an open-collector output transistor.

When the internal output transistor is ON, pin 8 is actively pulled LOW.

When the internal transistor is OFF, pin 8 becomes high-impedance (open).

In the given circuit, however, pin 8 appears to go HIGH when the TL494 output is OFF due to the external pull-up path provided by R7 from the input voltage (Vin). Kindly confirm whether this interpretation is correct.

2. Operation of R7, R9, VT1 & VT2 (Driver Stage)

My understanding of the driver stage is as follows:

R9 is connected between TL494 pin 8 and the base node of the driver stage. It limits the current drawn from the open-collector output of the TL494 and protects the internal transistor.

R7 is connected from the input voltage (Vin) to the same base node, acting as a pull-up resistor. This ensures a defined logic HIGH at the base node when pin 8 is in a high-impedance state.

VT1 (BD139, NPN) and VT2 (BD140, PNP) together form a complementary push-pull (totem-pole) driver stage. This stage level-shifts the TL494 output and provides sufficient current to drive the gates of the high-side P-channel MOSFETs with fast rise and fall times.

To check my understanding, I have summarized the expected operation in the table below:

TL494 Pin 8 State         VT1 (BD139)   VT2 (BD140)           PMOS Gate            PMOS State
LOW (output ON)             OFF                    ON                   Pulled LOW            ON (conducting)
High impedance (output OFF)ON                            OFF                  Pulled HIGH (≈ Vin)    OFF (cut-off)

Kindly confirm whether this table correctly represents the intended operation of the driver stage and the roles of R7 and R9.

3. Output Voltage Control (CV Loop)

In the error amplifier (voltage feedback) section:

One input of the TL494 error amplifier is connected to a reference voltage derived from the internal 5 V reference using a 4.7 kΩ / 6.8 kΩ divider, generating approximately 2 V.

The other input is fed by the output voltage through the R12–R13 feedback divider.

My question here is whether this stage should be analyzed as a traditional inverting or non-inverting amplifier, or whether it is more appropriate to treat the TL494 error amplifier as a high-gain comparator, which modulates the PWM duty cycle until the feedback voltage equals the reference voltage.

Any clarification on the above points will greatly help me in understanding the design philosophy and reasoning behind this circuit.

Thank you in advance for your support.

[MariuszD]

You understood correctly. In the places where you're having difficulty, the schematic is designed incorrectly.
R7 and R9 form a voltage divider needed to ensure that the Vgsmax of transistors VT3/VT4 does not exceed 20V when powered by 30V. With a 12V supply, Vgs will be too small. The voltage range should be from 17V to 30V.

Error amplifiers should have a frequency compensation circuit, but they don't. I expect the regulator won't be stable.

Designing frequency compensation circuits requires advanced mathematical knowledge. This part of the project is often missing in amateur designs. (pin3 not connected)

[MrAl]

Dear all,

I came across the below TL494-based power supply circuit on the web and started analyzing its operation. While going through the schematic, I am facing some difficulty in clearly understanding the design logic behind the selection and connection of R7, R9, and the driver transistors VT1 & VT2. I would appreciate your guidance to validate and correct my understanding.

1. TL494 Output Behavior (Pin

As per my understanding, pin 8 of the TL494 is the collector of an open-collector output transistor.

When the internal output transistor is ON, pin 8 is actively pulled LOW.

When the internal transistor is OFF, pin 8 becomes high-impedance (open).

In the given circuit, however, pin 8 appears to go HIGH when the TL494 output is OFF due to the external pull-up path provided by R7 from the input voltage (Vin). Kindly confirm whether this interpretation is correct.

2. Operation of R7, R9, VT1 & VT2 (Driver Stage)

My understanding of the driver stage is as follows:

R9 is connected between TL494 pin 8 and the base node of the driver stage. It limits the current drawn from the open-collector output of the TL494 and protects the internal transistor.

R7 is connected from the input voltage (Vin) to the same base node, acting as a pull-up resistor. This ensures a defined logic HIGH at the base node when pin 8 is in a high-impedance state.

VT1 (BD139, NPN) and VT2 (BD140, PNP) together form a complementary push-pull (totem-pole) driver stage. This stage level-shifts the TL494 output and provides sufficient current to drive the gates of the high-side P-channel MOSFETs with fast rise and fall times.

To check my understanding, I have summarized the expected operation in the table below:

TL494 Pin 8 State         VT1 (BD139)   VT2 (BD140)           PMOS Gate            PMOS State
LOW (output ON)             OFF                    ON                   Pulled LOW            ON (conducting)
High impedance (output OFF)ON                            OFF                  Pulled HIGH (≈ Vin)    OFF (cut-off)

Kindly confirm whether this table correctly represents the intended operation of the driver stage and the roles of R7 and R9.

3. Output Voltage Control (CV Loop)

In the error amplifier (voltage feedback) section:

One input of the TL494 error amplifier is connected to a reference voltage derived from the internal 5 V reference using a 4.7 kΩ / 6.8 kΩ divider, generating approximately 2 V.

The other input is fed by the output voltage through the R12–R13 feedback divider.

My question here is whether this stage should be analyzed as a traditional inverting or non-inverting amplifier, or whether it is more appropriate to treat the TL494 error amplifier as a high-gain comparator, which modulates the PWM duty cycle until the feedback voltage equals the reference voltage.

Any clarification on the above points will greatly help me in understanding the design philosophy and reasoning behind this circuit.

Thank you in advance for your support.

Hello,

I took a quick look and a couple things came up.

1.  VT1 and VT2
This looks like an attempt at an older style roll-your-own MOSFET driver.  This could work with lower frequency switchers, but it does not look like they did it right.  The problem looks like R9 is too large so that when pins 8 and 11 go low, VT1 is still in the linear mode.  That's not such a great idea because it could lead to a lot of overheating in both VT1 and VT2.  It should help a lot to reduce R9 to 22 Ohms or less, but you'll have to watch out for power dissipation in both transistors.  You may want to get ride of R8 also.  Better would be to use a dedicated MOSFET driver chip of some type.  If you insist on keeping the old style two transistor MOSFET driver, then look at that section separately in a circuit simulator to see how it operates.  When one transistor is on the other should be off.  If one transistor is on and the other is partially on the one that is partly on could get way too hot and burn up.

2.  CV Loop
The way these circuits normally work is the error amplifier is actually an integrator that integrates the error.  This means the output ramps up over several oscillator cycles.  As the output crosses the oscillator triangle wave the output switches.  That generates the PWM.  In this circuit they may be trying to rely on the speed of the op amp in order to get the result as a fast integrator.  This would be comparator-like but would still integrate.  The amount of that integraton effect may be too small though so most supplies will employ some type of compensation.  Compensation would come as a resistor in series with a capacitor, and that would be connected from pin 3 to pin 2.  The capacitor value would be 0.01uf, the resistor may be something like 27k to maybe 57k roughly.  That provides an action that is more like an integrator.  That could be the difference between stability and erratic operation.

3.  References
TI has several reference pages on this device so you may want to take a look.  One is slva001e.pdf available on the web.

4.  To zero in on all this you would have to do a simulation.

[MariuszD]

  The problem looks like R9 is too large so that when pins 8 and 11 go low, VT1 is still in the linear mode.  That's not such a great idea because it could lead to a lot of overheating in both VT1 and VT2. 

VT1 and VT2 are emitter followers, they can only work in linear mode. This is not a problem because capacitive load draws the current only when voltage changes.

[MrAl]

  The problem looks like R9 is too large so that when pins 8 and 11 go low, VT1 is still in the linear mode.  That's not such a great idea because it could lead to a lot of overheating in both VT1 and VT2. 

VT1 and VT2 are emitter followers, they can only work in linear mode. This is not a problem because capacitive load draws the current only when voltage changes.

Hello,

Well "linear" may not have been the best word for it.  The key point is that the transistors work in their active region which is not what we want if we want to mimic a switch with a transistor.  For example, if the power supply is 10v we don't want to supply the base with 5v, because that will cause more power dissipation.  A 10v supply with about 5v at the emitter means we have 5v across the transistor CE, and if there is significant current flow the power dissipation in the transistor will be high.
Regardless of what the current is, we still want the transistor(s) to behave more like switches than linear amplifiers.  To that end we supply the base with either 10v or 0v, not 5v.  We also get the full range of the output that way too.
In reality, when we supply 0v to the base we turn the transistor off, and when we supply 10v we turn the transistor on so the emitter output is a little less than that.
So it's still a voltage follower but we try to make it work more like a switch.

Now if we analyze the circuit at hand we find that the resistor values don't look right in order to get the two transistors to act more like switches.  Instead they look like amplifiers that amplify partial voltages, which we don't want.  We want as close to 'on' and as close to 'off' as we can get.

We do get a little help from R8 though, so I suggested doing a spice analysis to see how bad the situation really is.
This is not the usual way to use the old style two transistor MOSFET driver anyway.

There may also be a problem with the gate drive voltages when the power source goes up as high as it can go.  Do the gates get a voltage they can't handle.

[PGPG]

In the given circuit, however, pin 8 appears to go HIGH when the TL494 output is OFF due to the external pull-up path provided by R7 from the input voltage (Vin). Kindly confirm whether this interpretation is correct.

Correct

R9 is connected between TL494 pin 8 and the base node of the driver stage. It limits the current drawn from the open-collector output of the TL494 and protects the internal transistor.
R7 is connected from the input voltage (Vin) to the same base node, acting as a pull-up resistor.

Rather think of both R7+R9 being one pull-up resistor with output from its center.

VT1 (BD139, NPN) and VT2 (BD140, PNP) together form a complementary push-pull (totem-pole) driver stage.

It is not push-pull in the sense that once one transistor is switched on and in the second case the second.
R8 is the 'voltage follower' - it outputs the voltage from R7,R9 divider to MOSFET gates. This follower is reinforced by VT1 and VT2 when needed (it happens only when MOSFET input capacitance need be charged into one or second direction).

To check my understanding, I have summarized the expected operation in the table below:

TL494 Pin 8 State         VT1 (BD139)   VT2 (BD140)           PMOS Gate            PMOS State
LOW (output ON)             OFF                    ON                   Pulled LOW            ON (conducting)
High impedance (output OFF)ON                            OFF                  Pulled HIGH (≈ Vin)    OFF (cut-off)

Kindly confirm whether this table correctly represents the intended operation of the driver stage and the roles of R7 and R9.

True, but not 100%.
VT1 and VT2 are never ON in the sense they are saturated. They are never saturated. One of them conducts current (being in active mode (not saturated)) only during first short moment after TL494 output changes state.
So if your table tells about state that is stable in both states than you should for VT1 and VT2 have always written 'OFF'.

[PGPG]

The problem looks like R9 is too large so that when pins 8 and 11 go low, VT1 is still in the linear mode.  That's not such a great idea because it could lead to a lot of overheating in both VT1 and VT2.

I don't understand what you mean. Where from VT1 and VT2 overheating. Do you think that there are moments when they both conduct?
If yes than you are wrong.

It should help a lot to reduce R9 to 22 Ohms or less, but you'll have to watch out for power dissipation in both transistors.

With R9=22 you will burn MOSFETs for VIN=30V. Open their datasheet and see Vgs in 'Absolute maximum ratings' table.

You may want to get ride of R8 also.

Bad idea!
When you want MOSFET to be switched off it is better to set its Vgs to 0 then to 0.6V and this is ensured by R8.

If you insist on keeping the old style two transistor MOSFET driver, then look at that section separately in a circuit simulator to see how it operates.  When one transistor is on the other should be off.  If one transistor is on and the other is partially on the one that is partly on could get way too hot and burn up.

This once more tells that you probably think that there can be moments when they both conduct?
Vbe need be higher then 0 to make npn transistor conducting (pnp - lower than 0). When bases and emitters are connected together there is no physical possibility for both to conduct at the same time. Point.

So it's still a voltage follower but we try to make it work more like a switch.

Not in this circuit. Both transistors here work (alternately - never conduct at the same time) as voltage followers and after giving to the output the main portion of the charge they switch off (when current is too low to create a 0.6V voltage drop across R8).

[MrAl]

The problem looks like R9 is too large so that when pins 8 and 11 go low, VT1 is still in the linear mode.  That's not such a great idea because it could lead to a lot of overheating in both VT1 and VT2.

I don't understand what you mean. Where from VT1 and VT2 overheating. Do you think that there are moments when they both conduct?
If yes than you are wrong.

It should help a lot to reduce R9 to 22 Ohms or less, but you'll have to watch out for power dissipation in both transistors.

With R9=22 you will burn MOSFETs for VIN=30V. Open their datasheet and see Vgs in 'Absolute maximum ratings' table.

You may want to get ride of R8 also.

Bad idea!
When you want MOSFET to be switched off it is better to set its Vgs to 0 then to 0.6V and this is ensured by R8.

If you insist on keeping the old style two transistor MOSFET driver, then look at that section separately in a circuit simulator to see how it operates.  When one transistor is on the other should be off.  If one transistor is on and the other is partially on the one that is partly on could get way too hot and burn up.

This once more tells that you probably think that there can be moments when they both conduct?
Vbe need be higher then 0 to make npn transistor conducting (pnp - lower than 0). When bases and emitters are connected together there is no physical possibility for both to conduct at the same time. Point.

So it's still a voltage follower but we try to make it work more like a switch.

Not in this circuit. Both transistors here work (alternately - never conduct at the same time) as voltage followers and after giving to the output the main portion of the charge they switch off (when current is too low to create a 0.6V voltage drop across R8).

Hi,

Let's look at the first one.  Are they both on at the same time.

They probably won't be on at the same time, but during the transitions they might have to dissipate too much power.  This is because the MOSFET gate has significant capacitance, and the output of the two little transistors does not go from 0 to 30v it goes from maybe 15v to 30v with a 30v supply.  That means there could be 15 volts across both transistors and significant current during the transitions.

It's an interesting trick to get 1/2 of the voltage to drive the MOSFETs, but it should be checked.  In it's more usual form, it's also an old idea which is known to not switch the MOSFETs as fast as a dedicated driver chip can.

The main point was to do a simulation to check the operation of those two transistors and watch the power dissipation.
I've been trying to get this member to do simulations for the last year or more.  I don't think he likes to do that and it's an important thing to do when checking out a design, and also to find out how it all works.  Looking at the waveforms reveal a lot about the circuit, maybe not everything, but a lot.  That's why they make simulators.

I also addressed the problem of the output being too high with a source input of 30v (or even lower) which can drive the gates too hard.

Also, they are voltage followers there's no way around that.  All that means is that they can output a voltage that is not consistent with either power supply rail.  That means the power dissipation has to be checked. *period*.
If you still don't agree, then explain how we can get an output at the emitters that is nearly 1/2 of the supply voltage when pins 8 and 11 are at near ground potential.  We can't have an intermediate output voltage with transistors that act like perfect switches.

So the main point I was getting at was:
USE A SIMULATOR!

[PGPG]

They probably won't be on at the same time,

Not probably, but certainly. VT1 base has to be at 0.6V above emitters (both are connected together) to conduct. That means also VT2 base is 0.6 above emitters while it have to be 0.6 below emitters to make VT2 conduct. It is not only switched off by having Vbe=0 but by having it reverse polarized - one is 'perfectly switched off' when second conducts.

but during the transitions they might have to dissipate too much power.  This is because the MOSFET gate has significant capacitance, and the output of the two little transistors ...

Have you seen BD139 and BD140? Their parameters: 3A Ic peak (1.5A continuous), 1.25W without radiator (up to 12.5W with radiator).

...does not go from 0 to 30v it goes from maybe 15v to 30v with a 30v supply.  That means there could be 15 volts across both transistors and significant current during the transitions.

VT1 has easier - during pulse its Vce drops from about 7V down to 0 (voltage drop at R10, R11 is close to 8V).
VT2 has more difficult situation - during pulse its Vce changes from may be 22V down to 15V. So assume it conducts 3A with average voltage of 18.5V Vce all the pulse time.
IRF9540 Total Gate Charge is max 61nC. So 3A*t=122nC. t=40ns. So I assume 3A 40ns pulse with 18.5V Vce drop. I don't know frequency but let us assume 100kHz so 10us period.
This makes average power dissipation in VT2 be about 3*18.5*40n/10u=0.22W (5 times less than it can dissipate without any radiator).

it's also an old idea which is known to not switch the MOSFETs as fast as a dedicated driver chip can.

I'm not power designer. I'm not using power MOSFETs at all. But in this circuit (if R10, R11 will stay) I don't expect dedicated driver chip could switch MOSFETs faster.
I remember years ago reading some such driver specification and there were something about 1A output drive. May be there are other stronger but here VT1 and VT2 gives about 3A pulses (VT2 base is driven from 15V by 110R) and thanks to not being used as switches they are very fast as don't need time on going out of saturation.

The main point was to do a simulation to check the operation of those two transistors and watch the power dissipation.

And here we differs. I don't see a need to simulation.

I've been trying to get this member to do simulations for the last year or more.  I don't think he likes to do that and it's an important thing to do when checking out a design, and also to find out how it all works.  Looking at the waveforms reveal a lot about the circuit, maybe not everything, but a lot.  That's why they make simulators.

I treat each thread generally separately. In most cases don't remember who said what a week ago.

I've got PSPICE demo/student version at CEBIT in 1992. Demo = limited to 30 nets (single OpAmp precision model can probably use it up).
As I was used for years to design without any simulation (I have designed and build my oscilloscope in 1982) I didn't feel (and still don't feel) any need to use it.
When 10 years ago I moved from WinXP (32) to Win7 (64) my PSPICE refused to work. In KiCad there is Spice. About 2 years ago I spend one day checking that 'it works'. So if I will need it I will be able to, but during 2 years didn't had any need.
I was seriously very surprised seeing at KiCad forum that lot of people uses Spice. In my opinion simple circuits just works as you designed them and for more complicated I don't believe in models modelling reality enough close so prefer to make measurement.

[ommsiva]

Dear Sir,

When Vin =30V, the divider R7 & R9 will allow 15V as both resistor are equal. The current through voltage divider = 30/440= 68.18mA. this current is with in 250mA , which is 68.18mA current it can be sinked by open Collector TL494. We assume that 6mA(10 times lesser than 68.18mA)current flow through flows through R8, which makes voltage drop of (220*6mA)=1.32V. The output the driver would be around 15-1.32=13.68V.

The followings would be obtained

1. when base of Open collector transistor is low, the open collector Transistors  collector terminal will go high , since is has total resistance(R7+R9) 440 ohm & its sinks 68.18mA.

ANS:VT1 base voltage will be 15V and Emitter will be 13.86V. This guarantee that VT1 shall be in on Condition. Now VT1 is acting as emitter follower supporting extra current required for charging the gate of PMOS other than from R8. This current is transferred to the Inductor and Capacitive filter and Passed to output As voltage. VT2 will be OFF since emitter is at 13.86V and Base is at 15V.


2) when base of Open collector transistor is high, Open collector transistors collector terminal will be low. INternal transtor is off.

Ans: How to analyse this condition and Finally VT2 should be in on state to support the mosfet to switch off faster(provide a path to discharge gate Capacitance of mosfet) . How VT1 will be  in off condition? . I cannot conclude with this understanding.


3) VT1 has easier - during pulse its Vce drops from about 7V down to 0 . How sir it is 7 down to zero?


Correct me if my understanding is wrong.

[PGPG]

We assume that 6mA(10 times lesser than 68.18mA)current flow through flows through R8, which makes voltage drop of (220*6mA)=1.32V. The output the driver would be around 15-1.32=13.68V.

No.
Voltage drop B-E can't be 1.32V.

3) VT1 has easier - during pulse its Vce drops from about 7V down to 0 . How sir it is 7 down to zero?

You should read whole sentence - including "(voltage drop at R10, R11 is close to 8V)".
I will try to let you understand this, but I will not insert any drawings. If you want to verify if understood correctly draw schematic yourself and ask if is ok.

First step on the way to understand what I have written...
Forget schematic you started with and make new one, much simpler.
Take npn transistor. Connect its collector to +15V. Connect its base through 220 ohm also to +15V. Connect its emitter to GND (0V) through 2.35 ohm. Now assume Vbe=0.7V and Ic=99*Ib (so Ie=100*Ib) and using ohms law try to find voltage at base and emitter.

[ommsiva]

Dear sir,

Voltage across Base emitter junction will be -0.98V And Transistor will be in OFF Condition.

Attached the Image & Correct my Understanding.

[MrAl]

The main point was to do a simulation to check the operation of those two transistors and watch the power dissipation.

And here we differs. I don't see a need to simulation.

Power supplies are often looked at as 'simple' circuits but often problem sneak into the designs so a simulation is always recommended, as well as bench test and life test, and when needed tests at high line and low line as well as at nominal line.  In this case it would be for the entire input voltage range, probably the lowest, the highest, and nominal.
These tests are to verify the design operation as well as how it behaves thermally.

I've got PSPICE demo/student version at CEBIT in 1992. Demo = limited to 30 nets (single OpAmp precision model can probably use it up).
As I was used for years to design without any simulation (I have designed and build my oscilloscope in 1982) I didn't feel (and still don't feel) any need to use it.

That's old school.  Things have changed a lot since the 1980's.
The LT Spice simulator is free and a lot of people use it on the web.  It allows not only testing a design, but also sharing the simulation schematic so others can run it as soon as they download it.  If he uploaded that kind of file, we could all run it right this minute and see what is going on at every point in the circuit.
Don't get me wrong though, I never preach 'simulator' alone, I always say that circuit theory must also come with it.  There are some things a simulator can't easily show, and that means some of the theory will never be discovered using a simulator alone.  For circuit verification though it works out pretty well and almost everyone else I talk to uses a simulator.  It's a design tool and it's free, might as well us it.

[PGPG]

Attached the Image & Correct my Understanding.

Schematic is correct.
Your first equation is wrong so I don't read any further.
If Ve would be 0V then you will have Vb=0.7, but Ve is not 0V.

Generally in math if you at the beginning assume Vbe=0.7 and at the end get Vbe=-0.98 than your conclusion should be "we got a contradiction - such schematic can't exists "

This task need to write and solve more complicated equation.
Don't worry - keep trying.

I looked further....
When you get Ve=15.28 red lamp should light in your head. You can't have 15.28 while supply is 15.
In last equation you replaced Vb with 14.3 while in first you used Vb = 0.7. Be consistent.
If you want to learn electronic (really anything) you can't be so chaotic.
You should not overlook such obvious bugs.

[PGPG]

The LT Spice simulator is free and a lot of people use it on the web.  It allows not only testing a design, but also sharing the simulation schematic so others can run it as soon as they download it.  If he uploaded that kind of file, we could all run it right this minute and see what is going on at every point in the circuit.

I have tried LTSpice something about 15 years ago but was surprised that I have to write any texts at schematic. In PSpice (from 1992) I had everything set in menu. Using menu I don't need to remember format to be used. I also had a blocks with 1,2,3,4 inputs and voltage or current output and behavior described by equation (can be in s domain). Using such blocks makes schematic for me clearer than using labels and use them in equations. So I get back to PSpice. The 30 net limit was not important for me as if needed to check anything it always were very simple circuits.
Then in 2017 (WinXP->Win7 move) PSpice didn't went with me but I had no need since then. You have so many things you would like to learn (in my case Inkscape, GIMP, Python, FreeCAD, LTSpice,..) and you have no time. In 2017 I have read all KiCad manuals. They were titled V4 but really were about V3 what I learned when after reading them I downloaded and installed KiCad V4.0.7. Now, as I am using KiCad (last year - not) I think it would be time to read all them once more as there are probably many features I even don't know about. But the day doesn't want to have more than 24 hours

[ommsiva]

Yes Sir,

My thinking was initially influenced by a fixed-bias circuit analogy, even after completing the drawing. I was assuming that fixed bias is essentially an inverter with a poor stability factor. However, based on your explanation, I now realize where my understanding was incorrect.

I have corrected the mistake, and the updated details are attached for your reference.

The output voltage is given by:

Vo = Vreg (1 + 6.8k / 1k)

Where
Vreg = 5 × (4.7k / (4.7k + 6.8k)) ≈ 2 V

Therefore,

Vo = 2 × (1 + 6.8 / 1) ≈ 16 V

If a higher output voltage is required, increasing (approximately doubling) the potentiometer value would allow the output to reach around 30 V.

Please let me know if my understanding is now correct.

[ommsiva]

Dear Sir,

I would like to clarify the operating conditions of the PMOS transistors (VT3 & VT4) in our circuit.

When Output is LOW:

1)The voltage divider R7–R8 sets the bases of VT1 and VT2 to ~15 V.

2)VT1 emitter will be ~14.3 V, which is insufficient to turn on the PMOS.

3)VT2 remains OFF.

Result: PMOS transistors remain OFF.

When Output is High Impedance (Floating):

1)VT1 is biased through R7 and turns ON.

2)VT2 remains OFF.

3)The gate of the PMOS remains at nearly the same voltage as its source.

Result: PMOS transistors remain OFF.

When PMOS Will Turn ON:

The PMOS transistors turn ON when VT2 is activated and pulls the PMOS gates sufficiently LOW relative to their sources.

This occurs when the output is driven HIGH, allowing VT2 to conduct and reduce the gate voltage below the source voltage (VGS < Vth).

Summary:
The PMOS transistors remain OFF when the output is LOW or floating.

Correct me if i am wrong in my observation.

[MariuszD]

You don't know what the vce is, you can't calculate it like that. You can simplify the circuit by replacing the transistor with a resistance reduced by a factor of hfe
(beta). You can't accept 100 for hfe. You need to calculate two extreme cases: min hfe = 25, max hfe = 250.

This can be simplified by analyzing the moment after the TL494 output changes from low to high-Z.

And so, for a change, from high-Z to low

This equivalent schemacic allows you to calculate peak currents.

I would like to clarify the operating conditions of the PMOS transistors (VT3 & VT4) in our circuit.

When Output is LOW:

1)The voltage divider R7–R8 sets the bases of VT1 and VT2 to ~15 V.

2)VT1 emitter will be ~14.3 V, which is insufficient to turn on the PMOS.

3)VT2 remains OFF.

Result: PMOS transistors remain OFF.

It's important to distinguish between the transient state and the steady state.

In the steady state for the low output of the TL494, let's assume it's 0V. Then there's 15V across the divider and 15V at the gates as well. At R8, it's 0V and both transistors are cut off. It's different when we have a transient state, let's say the TL494 output changes from high-Z to low. Very shortly after the state changes, the voltage across the divider starts to drop, but the voltage at the gates is still 30V relative to ground. In this state, the B-E  junction of VT2 starts to conduct, and the collector-emitter circuit supplies a large current to the gates. In less than one microsecond, the gates will charge and the VT2 current will drop to zero.

[PGPG]

Please let me know if my understanding is now correct.

Your calculations are close to true but where from you get Vce=7.5V ?
You just assumed it and not calculated, I think.

You found the correct equation: 220*Ib+Vbe+2.35*Ie=15 and from it you can get everything.
As we assumed Ie=100*Ib you can replace Ib with Ie/100 and you get:
2.2*Ie+2.35*Ie=15-0.7
4.55*Ie=14.3  ->  Ie=3.14A
So voltage drop at 2.35 is 3.14*2.35=7.4V (so Vce=7.6V).

When I was writing that VT1 drops down from 7V and that at 2.35 you have 8V these values came from the following estimate.
Vbe is much smaller than 15V so I ignore it (Vbe=0).
Now Vce equals voltage at 220 but Ie=100*Ib. When you have the same voltage but 100 times higher current than it is like you would have 100 times smaller resistance. So you have voltage divider made of 220/100=2.2 and 2.35 ohms. So voltage is about 15/2=7.5 but at 2.2 little less (so I assumed 7V) and at 2.35 little more (so I assumed 8V).
All this can be simply made in your brain (not needing serious calculations) in few seconds.
Of course obtained result is not accurate but we rarely have in electronic anything accurate (hfe can vary a lot).

Now spend some time to understand how this analysed circuit corresponds to VT1 from your first post.
You seem to still not understand that in stable states (after short transition time) voltage drop at R8 is 0. Knowing that should help in finding this correspondence.

The equivalent/simplified circuit for VT2 is as follows:
Take pnp. Connect collector to GND (0V). Connect emitter through 2.35 ohm to +30V. Connect base through 110 ohm to +15V (if you put 30V at divider made by 220+220 you get at output 15V with internal resistance 220/2=110). As previously you can assume Vbe=0.7 and Ie=100*Ib.
Analyzing it you can find Vce of VT2 when it starts switching.

I know that you want to understand the whole DCDC circuit but in my opinion you should not go to more complicated circuits until you will have absolutely 0 problems with understanding such simple circuits like tranistor + 2 resistors. Now you certainly have a problems with them.

[MrAl]

The LT Spice simulator is free and a lot of people use it on the web.  It allows not only testing a design, but also sharing the simulation schematic so others can run it as soon as they download it.  If he uploaded that kind of file, we could all run it right this minute and see what is going on at every point in the circuit.

I have tried LTSpice something about 15 years ago but was surprised that I have to write any texts at schematic. In PSpice (from 1992) I had everything set in menu. Using menu I don't need to remember format to be used. I also had a blocks with 1,2,3,4 inputs and voltage or current output and behavior described by equation (can be in s domain). Using such blocks makes schematic for me clearer than using labels and use them in equations. So I get back to PSpice. The 30 net limit was not important for me as if needed to check anything it always were very simple circuits.
Then in 2017 (WinXP->Win7 move) PSpice didn't went with me but I had no need since then. You have so many things you would like to learn (in my case Inkscape, GIMP, Python, FreeCAD, LTSpice,..) and you have no time. In 2017 I have read all KiCad manuals. They were titled V4 but really were about V3 what I learned when after reading them I downloaded and installed KiCad V4.0.7. Now, as I am using KiCad (last year - not) I think it would be time to read all them once more as there are probably many features I even don't know about. But the day doesn't want to have more than 24 hours

Hello again,

Oh I completely understand the time factor for learning, I am facing that a lot too lately.  We'll just have to ask NIST to add more hours to the day

If we all used the same simulator, we could all share schematic files and that would make it easier for us to go over some design or another.  I realize though that everyone has their preferences.