EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: promach on December 14, 2020, 12:29:26 pm
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Could anyone help to explain why OR type Clock Gate requires positive latch ?
while AND type Clock Gate requires negative latch ?
(https://i.imgur.com/Xe0tpw4.png)
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A & B = !(!A | !B)
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What are you trying to describe from A & B = !(!A | !B)
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What are you trying to describe from A & B = !(!A | !B)
! means NOT operation
& means AND operation
| means OR operation
if you're dealing with inverse values, you can use OR. It will be equals to AND for non-inverted values.
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Wait, how is A & B = !(!A | !B) related to my question above ?
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In the top arrangement, with the active-low clock input, the circuit needs to ensure that a falling clock edge that propagates "enable" to the output of the flop doesn't cause a falling edge at the output of the AND gate. (That would present a falling edge on the "output" gated clock to appear very late (flop clk-out delay + gate delay) ) So, the enable is passed through on the falling edge. But the clock is already low so the output of the AND remains low. Then the output will follow the input clock until the disable signal propagates through the flop. But this again will occur after the falling clock edge and prevent a runt pulse. In both cases, treat the flop output as a "pass a rising edge" (OR) or "pass a falling edge" (AND) function.
The same logic applies to the rising edge example.
Though both of these should be treated with a great deal of respect. They aggravate clock skew problems and can give rise to very interesting and hard to diagnose bugs. (Namely -- "slow" chips work (chips from the slow side of the process distribution) and "fast" chips fail intermittently, even at slow clock rates. )
The choice of clock gating strategy is dependent on a whole lot of things -- design rules, process characteristics, product performance targets, design team expertise, and even design management. It's harder than they make it look in the movies.
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For AND-type clock gate:
(https://i.imgur.com/4J9y0KO.png)
(https://i.imgur.com/exkpsCj.png)
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I have two questions on set_clock_gating_check SDC command (https://www.design-reuse.com/articles/34973/low-power-high-density-clock-gate.html).
1. Why for setup check, AND, NAND gates use rising edge, while OR, NOR gates use falling edge ?
2. Why for hold check, AND, NAND gate use falling edge, while OR, NOR gates use rising edge ?
(https://i.imgur.com/zZ1Fkxv.png)