important frequencies in high speed digital signals

[tyblu]

I started derailing a topic, so I've recreated it here to avoid a full-fledged hijack.

USB 3.0 can burst up to 5 Gbps using 2 full duplex lines, according to the great Wiki. The two 2.5GHz signals will have to have to be treated as RF with important frequency components up to 10x their switch frequency, or 25 GHz. Maybe some of this cost covers a VNA? The device inputs will have to have a broadband match up to 25 GHz, or at least have a match characteristic simple enough for which to compensate. Seems wonderfully difficult to me!
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I know that one should consider digital lines at 10x their switching frequency when laying out power paths and signal traces (keep traces less than 1/10 of a wavelength), but what about when you're trying to take the TL effects into account? Do you really need all components within 10x (9x or 11x, really, as even components are 0) its switch frequency, or can you just match up to 5x (2nd fundamental)? ie: Is the 10x rule of thumb just for avoiding TL effects in PCB layout, or is it even more generalized, applying to RF design? Yeah, I know, go to RFCafe already.

[As an aside, I know that one should consider digital lines at 10x their switching frequency when laying out power paths and signal traces (keep traces less than 1/10 of a wavelength), but what about when you're trying to take the TL effects into account? Do you really need all components within 10x (9x or 11x, really, as even components are 0) its switch frequency, or can you just match up to 5x (2nd fundamental)? ie: Is the 10x rule of thumb just for avoiding TL effects in PCB layout, or is it even more generalized, applying to RF design? Yeah, I know, go to RFCafe already...]

I've been reading Howard Johnson's books and they've been very informative. I believe this is my understanding of his material:

For digital signals, what you need to worry about are the rise/fall times of the signals, as these are the actual high frequency content of your digital signals. He says: "Most energy in digital pulses concentrates below the knee frequency: 0.5/Tr", where Tr is the rise time. "The behavior of a circuit at the knee frequency determines its processing of a step edge. The behavior of a circuit at frequencies above Fknee hardly affects digital performance"

But then the question arises as to what the rise time of USB3 signals are. I don't know.

[tyblu]

I'm not sure what the author means by knee frequency -- maybe on a PSD graph for a single pulse? That is useful when you want to recreate the signal nearly exactly, for example in a DSO where BW must be >0.35/tr (RC-type rise/fall), but not so much when all you want to do is extract the logic levels. For example, a UART signal may only be transmitting at 9600 baud but have a rise time at the driver end of 2.2ns. This signal does not need to be over-sampled at 0.5/2.2ns=230MHz or 0.35/2.2ns=160MHz in order to read it, only about 20kHz (Shannon's theorem).

Of course, there is no reason to worry about matching loads to lines with a 'kHz signal, but say you had a 2Gbps signal (USB3.0) on a 2m-long full duplex twisted pair line going into a level shifting IC with high impedance inputs. This signal will have frequency components at (2n+1)*2GHz, where n is any integer (harmonic), and will fall off as 1.3/(2n+1). If the input is made to match only 2GHz signals it is essentially low-pass'ing out the rest, smooshing the square wave into a sinesoid'ish monster -- is this so bad? It'd say yes, as if it is being sampled at ~4GHz, it has a high chance of never reading a valid 1 or 0. If the input is matched to the next fundamental, 6GHz, though, then a ~4GHz sample rate will likely read the value in the 'ripple' area of the signals. Are these 'rippled' areas completely within the realm of valid logic?

Which brings up another question: what is defined as valid logic? I've been taught that valid digital output must be <10% or >90%, and valid digital input must be <40% or >60%. The fundamental (n=0; monster sinusoid) would probably pass as a <40% or >60% signal, but not a <10%, >90% one. Does this mean a flip-flop that accepts the lax input range would correct for poor input impedance matching?

[allanw]

What he means by knee frequency is the frequency at which signals must be passed in order to not increase the rise time. At very low baud rates, this isn't a good metric, but it makes sense for faster digital signals.

Also at high frequencies, transmitters use pre-emphasis and receivers use equalization to boost high frequency signals (transitions) while lowering the signal strength of constant voltage levels. This is to balance out the skin effect losses which depend on frequency. I believe this preserves the square wave of the signal. Something like this image:

http://i.cmpnet.com/planetanalog/2009/02/C0351-Figure3.15.gif

[tyblu]

That's right; I've seen it emphasis used in radio communications. I haven't had the chance to use eye diagrams before, but they seem to be pure genius. Pre-emphasis may be standardized, but what about the inputs? The 'equalizer' is tuneable, I imagine? And any idea what the minimum signal level needs to be at off-fundamental frequencies (ie: 6GHz for a 2GHz clock; eg. min -20dB tunable), or a part number with a decent datasheet?

[Time]

Take your rise time as a half period and model around that for a frequency.  Its probably more accurate than your fundamental.

[tyblu]

I assume you mean a quarter-period, but don't understand why, as that is similar to a sinusoid at the fundamental. And what you mean by accuracy?

[jahonen]

Knee frequency means where the spectral envelope starts to roll-off 20 dB/dec. This is about 0.35/tr for gaussian pulse shapes.

I have thought that for usual digital signals, the frequency doesn't actually matter for good signal integrity. If you can get one single rising/falling edge cleanly to the receiver, then the system works, regardless how many edges per time unit you do (=frequency). Thinking this from frequency viewpoint is IMO a "DC-handicapped" way. Frequency (memory bus for example) only affects the timing margins of a multi-signal system (intra-signal skew must be more tightly controlled).

RF people seems to be particularly fixated to the frequency thinking. That is of course natural since they usually work with narrow-band signals, where carrier frequency is relatively high (MHz-GHz range), but signal bandwidth is usually narrow compared to the carrier. It is valid assumption there that signal is "single frequency", thus you can speak of "xxx MHz" signal. Digital is other way around, carrier is DC but the signal bandwidth is from DC up to the knee frequency. Result is that spectral content of the signal does not obey the 50% square wave spectrum, exception of the clock signals, of course.

Where this frequency thinking fails, take a memory bus for example. It might be that some signal lines to be idle for relatively long but even when the "frequency" is low, the edge rate does not change. The signal must change its state fast enough when the "action" begins in the bus. So from the signal integrity point, one must use the edge rate as basis of the termination and other signal integrity requirements. If you have only 10% duty cycle, then the spectra is completely different, and the attenuation characteristic of harmonic components is quite different. PBRS assumption is more appropriate for data and address lines.

I have made several measurements on real digital signals using a spectrum analyzer. I'm actually quite amazed how few people take a look at their signals from this perspective. Scope can't usually show such wide bandwidth properly as FFT implementations are somewhat limited for very wideband measurements. It is not always that one can even see the knee frequency, as the pulse shape does not conform to the gaussian shape. For example here is a measurement of 27 and 125 MHz signals (markers tend to lie somewhat due to setting resolution). It shows that after initial attenuation, both signals have approximately same harmonic content. Lower frequency signal has only more harmonics. Some outputs have this knee more visible. For example, a 100 MHz clock signal from Cyclone II FPGA has this knee very well visible in around 3-4 GHz.

As data signals, like in USB and other similar stuff, the spectrum tends to resemble PBRS spectrum, where spectrum is continuous up to data rate, where the first null point is (excluding the clock leakage due to imperfections). Also, 900 MHz GSM base station tends to interfere a bit with this measurement (apparently rising around 950 MHz).

From information point of view, the frequencies below first null are important. The receiver on the high speed serial links (SGMII, SATA, USB, etc.) are usually combination of clock recovery and receiver (sampler). It is not practical or even possible to use the signals directly, due to imperfections. The clock recovery block recovers the symbol rate clock and adjusts the sampling point of the receiver to be in the middle of the eye opening, where we have the biggest difference between possible symbol states. So if we have sufficiently open eye, then we can easily recover the signal.

Regards,
Janne

[tyblu]

Excellent post -- 5 stars! Does this mean a designer doesn't have to consider matching their inputs for a 1GHz+ digital line?
I'll have to wait 'til sometime during the week to get my hands on ADS to try some of this out. Hope it has a PBRS block.

[saturation]

Yes, j's high speed insights are just marvelous.

Excellent post -- 5 stars! Does this mean a designer doesn't have to consider matching their inputs for a 1GHz+ digital line?
I'll have to wait 'til sometime during the week to get my hands on ADS to try some of this out. Hope it has a PBRS block.

[jahonen]

Excellent post -- 5 stars! Does this mean a designer doesn't have to consider matching their inputs for a 1GHz+ digital line?
I'll have to wait 'til sometime during the week to get my hands on ADS to try some of this out. Hope it has a PBRS block.

Inputs are matched in such cases. Newer chips have the termination resistor embedded in them, since external termination might be difficult to realize. In such cases, designer must not terminate the line separately. Just the traces must be designed so that desired impedance is realized. One big difference between microwave and digital circuits is that signal count in digital circuits is huge compared to typical microwave design. On the other hand, matching in microwave circuits is usually better, something like 20 dB return loss or so.

As a general rule, line termination should be done when round trip delay in the trace is greater than 1/20..1/5 of the rise time (I think it easier to think this way than through frequency!), depending how puristic one wants to be. So there are no hard limits. For most logic, and point-to-point connections, a series termination (resistor in series at the driver end) is a good solution. For such solution, reflection suppression occurs at driver end. One reflection happens at the end of the line, but that does not hurt the signal integrity. It really is shame that so many data sheets lack info of real rise/fall time, although it is crucial parameter, and can even determine if present solution works or not! For that reason, I tend to put series resistor in just about every signal, even if the termination is not actually required, a series resistor makes good access point in signals during debugging session.

Regards,
Janne

[Bambur]

Janne, terveisia Tre:lta! Would a series resistor actually do the matching or does it just load and damp the transmission line?

[Time]

You'll probably want a reactive matching network.  You'll essentially make a voltage divider with something purely resistive.

[jahonen]

Janne, terveisia Tre:lta! Would a series resistor actually do the matching or does it just load and damp the transmission line?

Nice to meet someone from Finland!

Yes, series resistor at the driver end matches the transmission line. Resistor must be chosen so that driver output impedance equals the transmission line impedance. How this will work is that there is 100% reflection at the load. When the signal arrives back to transmitting end after 2*tpd (propagation delay of the transmission line), the reflection will be absorbed by the series resistor and the driver output impedance.

This matching method can't be used if the line is multipoint, i.e. there are several receivers along the transmission line. This is because the match method will initially form a voltage divider with the transmission line impedance (transmission lines are basically resistive!), so that in case of perfect match, the voltage in the line will be half of the final value. That would mean that voltage would be at undefined level for significant period of time, creating logic hazard. See the attached picture. The end load will not see this, as the incident and reflected wave have same voltage there. Another advantage of this simple termination method is that there is no extra power drain, unlike in AC- and DC-terminations.

Reactive matching is not possible since digital signals are wide bandwidth (from DC up to aforementioned knee frequency). Reactive and other "magical" lossless match methods can only be used with narrowband signals, such as RF.

Regards,
Janne

[Time]

ah, I forgot this was a digital application.

[Bambur]

Thanks, Janne! I agree to your explanation and it makes a lot of sense.

Could you point out a method(s) for the multipoint case? Let's say we have a high-speed clock signal that should be distributed to several IC's. How the matching could be done in such a case?

[joelby]

Could you point out a method(s) for the multipoint case? Let's say we have a high-speed clock signal that should be distributed to several IC's. How the matching could be done in such a case?

Perhaps by using a low skew fan-out buffer?

I've used a NPN transistor to amplify a 100 MHz clock (generated by an FPGA pin) and then used a voltage divider, terminating to 50 R at each of the outputs. It was pretty fiddly to impedance match it correctly and get it working! A fan-out buffer chip would have been much easier to use, and wouldn't have been restricted to a single frequency.

[jahonen]

Thanks, Janne! I agree to your explanation and it makes a lot of sense.

Could you point out a method(s) for the multipoint case? Let's say we have a high-speed clock signal that should be distributed to several IC's. How the matching could be done in such a case?

Generally, this can be hairy business. Especially if you have timing constraints involved (system synchronous signals). Mentioned fan-out buffer is one (very good) method. But in simple cases it might be possible to feed 2-3 clocks from the same output (assuming it has acceptable drive strength), in such way that each branch has its own series termination resistor. All branches should have equal lengths, to avoid branch-to-branch reflections.

If you just want to clock several chips without any particular timing requirements, then you could make a low-impedance clock line using a resistive or AC-end termination. However, finding a clock driver which will faithfully drive something like 25 ? transmission line can be difficult. Low line impedance reduces the imperfections caused by each load. Therefore clock fan-out buffer is probably the easiest way to do the clock distribution. There are even "zero-delay" buffers which contain a PLL to zero out the delay involved with the buffer.

I can only recommend the Howard Johnson's book "High-Speed Digital Design", really anybody doing digital design (even if "low-speed") should read it. It has chapter about clock distribution.

Regards,
Janne

[Bambur]

joelby and Janne, thanks a lot for the answers! I'll try to get the book and read it.

tyblu, I didn't mean to hijack the thread. Anyway, I apologize for using it to post a couple of my questions.