Controlled impdance, JLCPCB vs KiCad calcs

[ifonlyeverything]

I'm trying to design my first controlled impedance PCB, a very simple USB isolator. This is USB 2.0 high speed so the spec is 90 ohms differential impedance. Signal will be on the top layer, followed by two inner ground pour layers, and an unused bottom signal layer. I punched this into JLCPCB controlled impedance calculator for JLC04161H-7628 stackup and I get this, a trace width of 0.1704 mm for the minimum supported trace spacing of 0.1016 mm.



I punch this into KiCad's calculator (H = L1 + Prepreg + L2, per the JLCPCB layout) and I get a estimated 110 ohm differential impedance. This is about 20% too high vs 90 ohms target.



To bring it down to 90 ohms I would need a trace width of about 0.306 mm. Who do I believe here?

[PeteH]

The height value for the kicad tool....
--- H = only the dielectric thickness between L1, L2.

Also note that the dielectric constant of the FR4 being used by JLC is probably closer to 4.1-4.2

[WatchfulEye]

Did you get the dielectric thickness right in kicad? H should be the thickness of the dielectric only, not the trace/ref plane - i.e. 0.21mm

Further kicad does not calculate the effect of solder mask, which can be substantial. Using my home-made field solver and JLCPCB's solder mask specifications, for this scenario the soldermask reduces impedance by around 7-8 Ω.

Results from my solver are (T = 0.035, W = 0.17, S = 0.10):
H = 0.26, No solder mask: 103 Ω
H = 0.26, Solder mask: 95 Ω
H = 0.21, No solder mask: 100 Ω
H = 0.21, Solder mask: 93 Ω