Controlling Mosfet from PG signal that is either low or high impedance

[onemanonelaptop]

Hi all,

hopefully someone can clarify my understanding here.


I have a dc/dc converter which has a power good pin defined in the datasheet as follows.

TPS63070 (https://www.ti.com/lit/ds/symlink/tps63070.pdf?ts=1704425648638)

output voltage above power good threshold = HIGH IMPEDANCE
output voltage below power good threshold, in thermal shutdown or input / output overvoltage protection active = LOW


What i want to do is turn OFF a mosfet when the signal goes HIGH IMPEDANCE and have the mosfet ON when the signal is LOW.

The mosfet i have on hand is a AO3401A (https://datasheet.lcsc.com/lcsc/1810171817_Alpha---Omega-Semicon-AO3401A_C15127.pdf)


Will this work as i intend? Or have i misundersatnd the PG pin's operation.




with a view to achieving something similar to this:

[berke]

What is connected to the output?

In general it's better to have the voltage rise slowly (but not too slowly.)

If you look at fig. 24 you see that a 1.5A pulse causes the output voltage to drop by 310 mV for about 50 µs.  The curve is for 7V but let's pretend the same thing happens at 5V.
The PG threshold voltage for falling Vout is 94.5% max, which would be 275 mV at 5V.

So when your PMOS turns on, if the inrush current is close to 1.5A Vout might drop enough to cause PG to become high impedance.  With the 645 pF input cap of the PMOS and the 100k ballpark the gate could fall below the transistor's max threshold voltage of 1.3V in about 50 µs, turning your load off.  Vout then rises and PG becomes low again.  If your load discharges quickly enough, you could get a 10 kHz ~5Vpp waveform, which is probably not what you expected.

[onemanonelaptop]

Thankyou for the reply, i always forget some context.

What is connected to the output?

the VREF output is connected to a voltage reference pin on another chip which i assume has a current draw in the low uA range, although i cant locate a datasheet but i cant see a voltage reference pin ever drawing much.

[Andy Chee]

the VREF output is connected to a voltage reference pin on another chip which i assume has a current draw in the low uA range, although i cant locate a datasheet but i cant see a voltage reference pin ever drawing much.

I feel there might be a better way to do what you want, by connecting the +5V to the other chip's voltage reference, and the PG directly to the other chip's EN/CS pin.

[onemanonelaptop]

Ok so i wired this all up and the PG turns on the MOSFET just fine. So the VREF rises to 5V and then drops to zero as i wanted, however i would really like to delay the pmos turning on by an arbitrary time delay so that VREF stays at 5V slightly longer...

[onemanonelaptop]

Here is the captured output of the Mosfet, i would like to persist its 5V output for longer than the 464us it currently stays hgih before it switches off.

Ideally i would like something in the range of 1 second. I realise i'm going to need another IC in the mix most likely but not sure what the best path to take is.

[onemanonelaptop]

Ok so ive got something mocked up as kinda working how id like, however its likely ive done something silly here. If anyone would be so kind as to give it an eyes over for potential issues id be appreciative.



Which according to circuitlab is giving me the outputs i want.

Holding VREF for a specific time before collapsing.
Delaying the 5V rail until VREF is high but before it collapses.





Circuit Lab circuit here.