What is connected to the output?
In general it's better to have the voltage rise slowly (but not too slowly.)
If you look at fig. 24 you see that a 1.5A pulse causes the output voltage to drop by 310 mV for about 50 µs. The curve is for 7V but let's pretend the same thing happens at 5V.
The PG threshold voltage for falling Vout is 94.5% max, which would be 275 mV at 5V.
So when your PMOS turns on, if the inrush current is close to 1.5A Vout might drop enough to cause PG to become high impedance. With the 645 pF input cap of the PMOS and the 100k ballpark the gate could fall below the transistor's max threshold voltage of 1.3V in about 50 µs, turning your load off. Vout then rises and PG becomes low again. If your load discharges quickly enough, you could get a 10 kHz ~5Vpp waveform, which is probably not what you expected.