EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: muktupavels on May 01, 2018, 05:52:55 pm
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I am trying to create controller for LED display (p10 hub12 led modules). The main/biggest problem is that I have no knowledge in electronics (probably not exactly true at this point). The whole thing consists of following parts:
[PC] -> [A male to B male USB cable] -> [USB to RS485] -> [shielded cat5e cable] -> [Controller] -> [LED display]
I have managed to write PC software, create USB to rs485 adapter and controller in way that does work in my home, but it did not work as expected when test controller was connected to real display. There was two visible problems:
- communication with controller somewhat worked once and then it completely stopped working.
- controller restarted at random times.
First cat5e cable shield is not connected, I expect that this is one of all problems. Otherwise my guess is that problem is noisy environment (car service). Trying to communicate with controller RX led was blinking too fast and received data was not usable. The only way I could reproduce something similar at home is plugging monitor or notebook power adapter into extension cord in way that produces sparks.
Searching I found that I might need pull-up resistor for reset pin. By adding it controller no longer restarts (in way I was able to reproduce it without resistor). Controller was saying that it was external reset and datasheet says that RESET pin has internal pull-up resistor. Why does extra pull-up resistor seems to solve restarting problem?
Both PCBs are single sided and are created so I could etch them at home. Are PCBs created so badly that I am just lucky that it works? The end goal is to use double sided boards (home etched boards was meant only for testing), any recommendations with what should I keep in mind when I will try to redo PCBs with two layers?
Help is needed with shielding, it is currently unconnected, because I simply have not understood how to do it / seems that there are multiple ways to do it... On USB to RS485 I have added place / option to connect shield to GND with small capacitor. I really have not understood if that is good way to do it. If I understand correctly then shield should be connected only at one end so it seems that I should connect shield at controller side, because usb device might be unconnected and then shield would not be connected or that should not be problem?
What should I do with extra / unused pairs in cat5e cable? Is it ok to leave unconnected them? Reading about RS485 somewhere I read that unused wires should be connected to GND with resistor, unfortunately seems I have not saved link about it.
Do I need to provide any extra info?
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In regards to RESET - it's usually not sufficient to have only internal pull-up enabled, usually you would have something like this, with a button, for a RESET to work properly and to have a bit of debouncing for push-button. Pull-up is usually 10k-100k, but with this MCU I used a much higher one because MCU allows to do so and this is ultra low-power design. Basically, this is based on Atmel's reference designs for their evaluation boards.
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I'd strongly recommend you to connect the USB and CAT5 cable shields to GND, using a solid ground plane, on both ends. One can see often other strategies to connect the shield, from my experience the solid GND connection is the only one that works reliably. Maybe (depending on your setup) an isolation may be required to break a ground loop from the PC to the LED display.
For the unused pins of the CAT5 cable, one could connect them to GND, or just leave them open. More GND is most cases a good choice.
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In regards to RESET - it's usually not sufficient to have only internal pull-up enabled, usually you would have something like this, with a button, for a RESET to work properly and to have a bit of debouncing for push-button. Pull-up is usually 10k-100k, but with this MCU I used a much higher one because MCU allows to do so and this is ultra low-power design. Basically, this is based on Atmel's reference designs for their evaluation boards.
I don't use reset button, only thing that is connected to RESET is PDI. I have no problem adding pull-up resistor, 10k seems to work, but I would like to understand what might have caused RESET pin to go bellow 1.32V to trigger RESET. Or maybe it is not only RESET pin, but all power has dropped too low? But then should not chip report that it was brown-out reset not external?
I guess I should remove pull-up and make sure that brown-out is enabled and see if controller will report now that it is brown-out reset not external reset...
I'd strongly recommend you to connect the USB and CAT5 cable shields to GND, using a solid ground plane, on both ends. One can see often other strategies to connect the shield, from my experience the solid GND connection is the only one that works reliably. Maybe (depending on your setup) an isolation may be required to break a ground loop from the PC to the LED display.
Well almost every time I read about and RS485 I see that shield should be connected only at one end. So I am even thinking about using unshielded connector at USB to RS485 adapter side to make sure that it is never connected at both ends.
Also the problem is that I have not understood how to properly connect shield to GND, because it seems that I should not connect it directly to GND. Is small cap "right" thing to do?
For the unused pins of the CAT5 cable, one could connect them to GND, or just leave them open. More GND is most cases a good choice.
So one pair for A and B and all other directly to GND?
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Yes, that's quite strange, I've checked the manual and it says "The RESET pin includes an internal pull-up resistor" and it's a 25kOhm resistor, which is more than enough to keep it steady. You can check reset status register after such reset occurs to see the cause of it. Maybe that was a WDT reset? I got cought by that when I was starting with Atmel SAM devices, WDT was enabled by default and was resetting the device every 16 seconds.
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You can check reset status register after such reset occurs to see the cause of it.
That is how I know that it is external reset. :) Thinking more about it it seems that there is no need to test if I get brown-out reset. If whole pcb has too low voltage then pull-up would not help...
What kind of things happens with voltage and/or current when there are some sparking when connecting other devices?
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If that was a BOR reset or POR - status register would have that, but you're saying it shows External reset, which means power was ok. Maybe RESET line pull-up is not enabled in fuses (if it can be enabled in there, I never worked with ATMEGAs) as that line is shared with PDI?
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I'd strongly recommend you to connect the USB and CAT5 cable shields to GND, using a solid ground plane, on both ends. One can see often other strategies to connect the shield, from my experience the solid GND connection is the only one that works reliably. Maybe (depending on your setup) an isolation may be required to break a ground loop from the PC to the LED display.
Well almost every time I read about and RS485 I see that shield should be connected only at one end. So I am even thinking about using unshielded connector at USB to RS485 adapter side to make sure that it is never connected at both ends.
Also the problem is that I have not understood how to properly connect shield to GND, because it seems that I should not connect it directly to GND. Is small cap "right" thing to do?
One can often read what you said you read. It's simply wrong for most applications.
Connect the shield as solid as possible to GND and if applicable, to your metallic chassis. If you don't have a metallic chassis or enclosure, it is even more important to tie the shield to GND solidly. Use no components in series with this connection, make a really bold connection.
For the unused pins of the CAT5 cable, one could connect them to GND, or just leave them open. More GND is most cases a good choice.
So one pair for A and B and all other directly to GND?
If you don't need the other pairs for other signals, that would be OK, or just leave them open. But you should at least have one connection for GND within your cable (as you did in the original plan).
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I have redone controller part. My I ask for some PCB layout review? Anything that is obviously wrong? Or any suggestion on how I could improve it?
Changes:
- removed all 0 ohm resistors that was used as jumpers
- added 10k pull-up resistor for RESET pin
- RJ45 shield and unused wires are connected to GND
- Removed second SN74LVC8T245
- Removed pins for keyboard
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I'd created a solid ground plane on both sides of the board. Also, have a look at this article in regards to bypass capacitors.
https://electronics.stackexchange.com/questions/74509/how-to-place-decoupling-capacitor-in-four-layer-pcb
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One more thing - it's best to have a 'star' or 'single point' power traces design, coming from same point, while yours are almost all serial, that leads to higher resistance, impedance and antenna effect, have a look at these articles:
https://www.maximintegrated.com/en/app-notes/index.mvp/id/3630 (https://www.maximintegrated.com/en/app-notes/index.mvp/id/3630)
And this one is the best, I think, have a look at 2.2.2
http://www.ti.com/lit/an/szza009/szza009.pdf (http://www.ti.com/lit/an/szza009/szza009.pdf)
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I'd created a solid ground plane on both sides of the board.
Why? What do I gain by doing it? Or what problems I could have not doing it so?
Also, have a look at this article in regards to bypass capacitors.
Thanks for your reply. May I ask at least for little explanation what is wrong with way I have done it or why it is wrong. The linked question itself is about capacitor placement on 4 layer PCB, but I use only two layers (not sure if that changes anything, I have not read comments and answers yet).
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Ground plane is basically a big shielding, it reduces any EMI effects and also structurally it makes the board more sturdy as most of the copper stays on it. In regards to power lines - you've got a very long power trace going from one current user to another, each trace has resistance and impedance, so effectively after each device that consumes current you're getting a small voltage drop, as any trace has resistance. Also, any trace has impedance and capacitance and impedance is basically acting as a resistor, trying not to change magnetic field and thus not allowing for current to flow, this also reduces current. Yes, it's all very small values but it's still not recommended to have a power trace, that's why we have 4 layer boards - basically they have signal traces on both sides and then a solid ground and power planes in the middle.
In regards to bypass capacitors you should take into account the same - your power traces design is in series and if your MCU is switching it's outputs fast and you connect VCC points from bypass cap to next bypass cap on next chip and so on - capacitors may not charge fast enough and that would cause troubles for MCU as it will not have enough power. Bypass caps are basically devices that can provide current fast when it's required. Here's another example from TI about bypass layout. In your case you can just put traces up and down from the cap, not sideways, as you did. Also, if you have ground plane on top (don't forget to put multiple vias connecting it to bottom ground plane) - you just need to connect power line and the other end of capacitor will have perfect connection to ground.
http://slideplayer.com/slide/4662087/15/images/31/Bypass+Capacitor+Routing.jpg (http://slideplayer.com/slide/4662087/15/images/31/Bypass+Capacitor+Routing.jpg)
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Have a look at this picture too:
https://i.stack.imgur.com/rRCDN.png
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And another good example why you would want to have a signal layer GND plane. Also, by the way, it dissipates heat very well, so, for example, for all my LiPo charger designs I'm always using GND planes on both sides with as many vias as I can put close to charger IC and power polygons instead of just traces. Here you can see a 'Signal ground' which is just a top ground plane, and you can see VCC lines for capacitors.
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You can have a look at my project here:
https://workspace.circuitmaker.com/Projects/Details/LtFlash/Sandwich-Battery-Charger
There is a release documentation down below so you can see schematic and PCB but here's an example of bypass caps ties directly to ground plane on one side and to power polygon on another, capacitors C3, C4, C5, C6 and C7.
And pretty much any device on this PCB that requires ground connection is directly attached to the top ground plane, which is very useful, you don't need to think about best ground trace layouts and connection is rock-solid.
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In your case you can just put traces up and down from the cap, not sideways, as you did.
Not sure if I understood this part... :( Anyway, I tried to redo power traces. Should I try to keep traces on top or it is better to route at least some power traces on bottom side?
Also your linked images shows something very similar how I have placed capacitors so I don't get what is wrong with them. :( Or was it because of power traces?
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The power looks very good now. In regards to bypass caps - I meant it has to be like C15 on your PCB, with a single shortest possible track to power and to ground and as close as possible to MCU pins. C7 and C17, for example, are not optimal because their ground traces are bent. With C7 - why did you put that trace sideways anyway? There's plenty of space to put it directly below the cap! That's why I posted this picture, for example:
https://i.stack.imgur.com/rRCDN.png
Also, if you'd have a GND plane on top layer - you wouldn't need vias to the back of your board. For bypass caps one of the links I showed before says 'Preferably there should be no vias for bypass caps and they should be located on the same side of the board where IC is'. Of course, on these low frequencies it would work anyway, but you've asked about good design. As to my opinion - GND planes on both sides are good, they're shielding your board, providing easy connections - you don't need vias or traces, they act as heatsinks and so on. The less vias you have - the better, ideal design would use just a single side of your board.
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Also, you can replace all the power traces past voltage regulator with a big power polygon. Any CAD would just make cutouts in that polygon for traces and you just need to rearrange them so they don't break the polygon, or make the polygon not square, but with many points. Again - that's better because it won't act as an antenna picking up EMIs and impedance would be much lower. And on top of that polygon just draw a square one covering the whole top side of the board for GND. That would actually simplify your design even more. But, of course, that's up to you :) Just my opinion.
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Also, if you'd have a GND plane on top layer - you wouldn't need vias to the back of your board. For bypass caps one of the links I showed before says 'Preferably there should be no vias for bypass caps and they should be located on the same side of the board where IC is'.
Ok, removed vias and put also gnd plane on top layer. Is that really better? Now GND plane under atxmega chip is almost completely separated from remaining gnd plane on top... Also I think I read that traces should first connect to capacitor and then to pins, but now gnd first connects to pins and only then to capacitor (C7, C16).
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Just have a look at connection width to ground plane now under ATMega chip and compare it to several small vias that were there before. Also, just to make sure, you can add more vias to bottom GND plane under the chip, just to be sure you're safe :)
In regards to capacitors - in the example picture I've shown there was a ground trace going to via under the chip and that's not good, of course. In your case - you've got a solid connection to ground, so it's good path for current to flow.
Now, after you've put the solid ground plane you can see there are still gaps in top ground like ones near IC3. You can either put vias to bottom ground plane in this case or rearrange your traces so they would be closer to each other to resolve this issue. The same with MAX3468 - rearrange traces so GND plane can fill the space, add vias to GND near bottom connector. And also, this is my personal preference, but I prefer to use solid joining of polygons to components, not the 3-point joint like you've done. Effectively you've created three thin traces to each ground from ground plane. You can usually change this in polygon settings. Nothing too bad about this as it's still a good solid connection, just my preference.
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By the way, you still need several vias from top ground to bottom one, that's important, as they must be well connected to each other! Usually you put some vias in corners of the board, but not too close to the sides, and also, of course, you put vias in the middle to fill all the gaps and usually under the chips too.
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Is there any recommendations or something like that about vias? How many do I need? Is one via under chip enough? Centered?
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If you want to go this route (placing vias all over the board), I'd recommend to place them in a raster (maybe 5mm ... 10mm). IMO this isn't necessary for this kind of circuit, but won't harm anyway. Another good thing to look where to place the vias: If a plane (no matter which side of the board) is slotted by one or more traces, place vias left and right of these traces, to the plane on the other side will connect over the slot.
From my experience, this board looks good enough, though it may be a good excercise to go all the way. I'm more concerned about the other board, you should do the same style redesign there.
Anyway (another IMO), I wouldn't have redone the board, but in the first place just bodged some solid ground connections across the existing boards (most important would be to solidly ground and tie together the USB and RJ45 shields) to see if this strategy helps (has done quite often).
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Usually it depends on how much current is going from VCC to ground. In your case it's a low-power board, so you don't need too many vias and they not necessarily should be under the ICs. You put vias under ICs usually under QFN ICs that have a thermal pad under them, like LiPo chargers or DPAK MOSFETs. So, just put several vias about 1cm away from corners of the board and you should be fine. And, just to be sure, you can add some vias where ground planes are not looking too solid. And I'd add vias everywhere where traces have broken your GND plane just to refill it.
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I have updated both boards. In both boards I tried to use polygon for power, is that good or in this case traces was better? In USB to RS485 both shields are now connected to GND. How boards looks now?
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Now they look very nice to me! Good job putting these VCC polygons in and forming a good GND planes! You can extend VCC plane just a bit so it would connect directly to IC1 output and covering C15. Same with all component connections - you can just extend your VCC poly to cover all the contacts of resistors and capacitors, like R3,R5 and C5 can be covered by extended VCC poly instead of connecting them with a trace. And, as I said before, it would be even better if you'd use straight join instead of 3-point one.
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And, as I said before, it would be even better if you'd use straight join instead of 3-point one.
You mean thermals? From what I understand they are used to make soldering easier. If that really helps then I would prefer to keep them. I don't have good temperature controlled soldering iron.
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And, as I said before, it would be even better if you'd use straight join instead of 3-point one.
You mean thermals? From what I understand they are used to make soldering easier. If that really helps then I would prefer to keep them. I don't have good temperature controlled soldering iron.
I'm talking about polygon connect style. You're using 'Relief connect' and yes, that helps with soldering, but you really don't need any good temperature controlled iron to solder even direct connect. I'm not using my reflow gun when soldering any types of components except for BGA or QFN ones, I'm using just a soldering iron. Usually you just put some flux on one contact of resistor/capacitor/other component, solder it, using twizzers to align component, and when you're happy with alignment - just remove iron from component while holding it with twizzers, let it cool down so it holds, and then just solder another contact pad of component. And I never had any issues using direct connect polygons and soldering components with just a simple cheap soldering iron. Yes, that would take a bit more time to heat up because of polygon plane, but nothing bad would happen. But again - that's up to you, I've seen many designs where relief connect is used, as an example - Atmel's evaluation boards, like ATSAM Xplained series and others.
Here's a link to connect styles in CircuitMaker:
https://documentation.circuitmaker.com/display/CMAK/PCB_Dlg-PolygonConnectStyleRule_Frame((Polygon+Connect+Style))_CM
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Here's how a board with direct poly connects looks like. Also note the full GND plating on top, how C5 and L1 are connected together with a polygon and a couple of polygons for VCC and other voltages on the right.
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Thanks! I decided to keep things as is for now. I am using EAGLE and it seems that your mentioned "Relief connect" is same thing as "Thermals" in EAGLE. :)
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No worries at all! :)
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First, a decoupling capacitor isn't needed on the DS3231 Vbat supply unless it is the only power source, Ie Vcc not connected. If it is just used for battery backup then there is no need for it. In fact having a decoupling capacitor there will drain the lithium backup battery faster.
I was looking at that long +5VDC trace. If you swapped the battery and clock with the logic level converter and atmel, and rotated the logic level converter 90 degrees, the length of the +5VDC trace would be roughly halved. Also the heavy 3.3VDC user, Atmel, would be closer to the power supply.. The clock chip uses so little power it just needs a bypass capacitor for it to be happy with it's power supply trace. I routinely power them using 5+ inch long 30 AWG VCC and GND wires with no reliability issues. The I2C carrying traces going to the Atmel can be long if needed. Just keep them the same length. On the other hand the +5VDC trace powering the logic level converter gets a workout when the LEDs are being updated.
If you need the time to be maintained for more than a couple days, feel free to ignore this. Another change I would make is swapping in a 0.47 Farad super capacitor in place of the lithium battery. A 3.3V or higher voltage super capacitor can be charged from the 3.3VDC supply using a diode, and resistor in series. The diode should have a very low forward voltage drop, and low reverse leakage current. Diodes with a reverse leakage current of 10 micro amps or less do very nicely. Search first for low forward voltage drop, then sort on increasing leakage current. Leakage currents down into the pico amps are available, but they often have relatively high forward voltage drops and cost much more. Size the resistor to set the maximum initial charge rate when the super capacitor is at 0 Volts with no charge. I use 25 to 50 mA. The charge rate will slowly lower as the super capacitor's voltage increases. It will charge up to 3.3V minus the diode forward voltage drop for < 1 mA current over a few hours. I've been using a diode that only has 0.3V drop at very low mA currents. A 2.95 Volt charge in a 0.47 Farad super capacitor will backup power the DS3231 for 2 to 4 days before it drops below the minimum voltage new temperature correction adjustments will still be calculated. My tests show the oscillator will keep working down to just under 1 Volt which takes a few more days to reach. It just looses adjustments to the temperature adjustments. 2 days should weather most power outages. Yeah, it's not years like a lithium battery, but it can be shipped with no lithium battery restrictions.
The super capacitor I've been using for my clock backup circuits is also able to be reflow soldered. No hand soldering or installing a lithium battery later. The main downside is cost. At $5.60/Q1, $3.32/Q200, the super capacitor is much more expensive than a coin cell lithium battery.
This diode CFSH05-20L from Central Semiconductor Corp is better suited than the one I use. Only 0.16V forward voltage drop at sub 1 mA currents. I may switch to it or another one.
https://www.centralsemi.com/get_document.php?cmp=1&mergetype=pd&mergepath=pd&pdf_id=CFSH05-20L.PDF (https://www.centralsemi.com/get_document.php?cmp=1&mergetype=pd&mergepath=pd&pdf_id=CFSH05-20L.PDF)
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May I ask for some review, again?
Some changes:
- ATXMEGA256A3U replaced with ATSAMD51J20A.
- Removed decoupling capacitor from DS3231 vbat.
- Added crystals.
- Added DS2482S.
- Added M95256.
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Pullup on SWCK is usually 1k as per SAMD21 or SAML21, make sure 10k is the correct one.
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Thanks! Data-sheet also says 1k. :)
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No worries, otherwise looks much better and professional! But I didn't check it thoroughly as I'm currently not at home :) Maybe just cover 3V3 output of the regulator with polygon? Till the middle of capacitor, as that's your primary 3V3 joint.
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Also it may be a good idea to add a lot of thermal vias around and under voltage regulator for better thermal performance.
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Just one more thing, I can see you've got a 5V trace running from connector, why don't you flip C7 upside down and then create a solid polygon for 5V rail? Just a thought, though. In regards to 3V3 rail - you often have different cover of the polygon over capacitor contacts, like at C1 or C5 - it's just a tiny 10mil trace, actually, even though you have a whole huge polygon next to it. Just cover the half of capacitor with that polygon everywhere, right to the middle of each cap, not the way you have it - different for each capacitor, that'd be good. Otherwise - seems good to me. Polygons can be optimized a bit, but nothing to be stressed about.
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Here's a good video from Dave about bypass caps and where to place them, just for information.
https://www.youtube.com/watch?v=1xicZF9glH0 (https://www.youtube.com/watch?v=1xicZF9glH0)
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Just a thought, though. In regards to 3V3 rail - you often have different cover of the polygon over capacitor contacts, like at C1 or C5 - it's just a tiny 10mil trace, actually, even though you have a whole huge polygon next to it. Just cover the half of capacitor with that polygon everywhere, right to the middle of each cap, not the way you have it - different for each capacitor, that'd be good. Otherwise - seems good to me. Polygons can be optimized a bit, but nothing to be stressed about.
The short traces between solder pad and flood fill polygon* is done is for easier soldering, and if mass produced it would be much less likely to have gravestones. Electrically it means very little because the traces are so short.
* I forget what they are called.
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Just a thought, though. In regards to 3V3 rail - you often have different cover of the polygon over capacitor contacts, like at C1 or C5 - it's just a tiny 10mil trace, actually, even though you have a whole huge polygon next to it. Just cover the half of capacitor with that polygon everywhere, right to the middle of each cap, not the way you have it - different for each capacitor, that'd be good. Otherwise - seems good to me. Polygons can be optimized a bit, but nothing to be stressed about.
The short traces between solder pad and flood fill polygon* is done is for easier soldering, and if mass produced it would be much less likely to have gravestones. Electrically it means very little because the traces are so short.
* I forget what they are called.
Yes, I know what relief connect is for, but usually you would want to pour polygon around pad so there would be three short traces to polygon from a pad. It may be important for power rails.
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Maybe just cover 3V3 output of the regulator with polygon? Till the middle of capacitor, as that's your primary 3V3 joint.
Did I understand this correctly? Please check new attachment...
Also it may be a good idea to add a lot of thermal vias around and under voltage regulator for better thermal performance.
Added only under regulator, is that ok?
Just one more thing, I can see you've got a 5V trace running from connector, why don't you flip C7 upside down and then create a solid polygon for 5V rail? Just a thought, though.
Is not trace big enough?
In regards to 3V3 rail - you often have different cover of the polygon over capacitor contacts, like at C1 or C5 - it's just a tiny 10mil trace, actually, even though you have a whole huge polygon next to it. Just cover the half of capacitor with that polygon everywhere, right to the middle of each cap, not the way you have it - different for each capacitor, that'd be good.
Done. Is that what you meant?
Here's a good video from Dave about bypass caps and where to place them, just for information.
https://www.youtube.com/watch?v=1xicZF9glH0 (https://www.youtube.com/watch?v=1xicZF9glH0)
Thanks, but I have seen that video. :) The real question is whether I have learnt something from it... Probably should watch again.
In few places I have put vias to connect top gnd polygons that are split by 3v3. Is that needed?
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Yes, you did understand correctly, now you have a solid 3-wire connections for each 3V3 rail! Thermal vias are good too, there's a solid polygon around that regulator and now with thermal vias even if regulator would get hot - these vias will help to dissipate heat. In regards to 5V rail - yes, trace is usually enough, I just got used to use polygons where possible with power rails, usually that's better, it also dissipates heat and has better conductivity too. In regards to GND vias - usually you would want to have them as that shortens your current return path, thus reducing impedance of a trace.
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Just one more thing - you probably would want to cover pin 3 of regulator with 3V3 polygon, that's why I included Dave's video, it says that you should have decoupling capacitor as close to regulator output as possible even if that's a polygon pour, but in your case it's just a short thick trace and then a huge polygon, so current would flow through that trace first. It's better to have a polygon and a cap close to the source of current, as I suggest.
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Sorry, my mistake, you're doing a thermal relief connection style for polygons, in that case - no need to cover pads with polygon as it will produce three thinner connections instead of your beefy one! I just so got used to have direct connect style that I'm making such stupid mistakes :)
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And another though - because you've got such a big 3V3 polygon and just a single connection from regulator - you may want to put some beefy tantalum cap somewhere on 3V3 rail, something like 47uF or 22uF or at least 10uF - that would help to keep 3V3 steady in case when fast switches of levels are generated by MCU, for example and would smooth output ripple of regulator. I'm not sure how much current would your board draw but usually it's a good idea to have such cap on 3V3 or any other power rail along with bypass cap (100nF - 1uF).
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Final thought, I'm not sure if you have checked this document yet, but here's a full design documentation for SAMD51/E54 Xplained Pro board, I'd choose same decoupling caps on all the pins of the MCU to guarantee it's stable performance. I'm not saying your design is incorrect, but maybe you just want to check it against a real production board that uses such MCU. That's what I usually do in my designs. Hope this helps!
http://ww1.microchip.com/downloads/en/DeviceDoc/SAM_E54_Xplained_Pro_Design_Documentation.zip (http://ww1.microchip.com/downloads/en/DeviceDoc/SAM_E54_Xplained_Pro_Design_Documentation.zip)
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Just out of curiosity - why did you choose such a powerful and complex MCU? Do you really need it? Because there are models like SAMD21, SAML21 in a 32-pin package and with 48MHz and full-speed USB onboard, or even in a SOIC-14 package, if you don't need to many GPIO ports. Easier to do a PCB for these ones, easier to debug and with almost all features. FPU is great and 120MHz too, but as far as I understand - you just need to talk to RS485 bus and to display, I2C and SPI buses? All that can be achieved with SAMD2x/L2x MCUs without any trouble. Also, external crystals are only required if you really want a high-precision stability, from my experience I had no issues to use internal oscillators of these MCUs, didn't notice any significant (to my applications, including FreeRTOS) time drift, but they allow to save a lot of power if you're operating from a battery or switched into a battery backup mode. SAML-series MCUs are the best for lowest power applications. In regards to external crystals - you also want traces to them to be as short as possible and of equal length for best stability.
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In regards to GND vias - usually you would want to have them as that shortens your current return path, thus reducing impedance of a trace.
Thanks!
And another though - because you've got such a big 3V3 polygon and just a single connection from regulator - you may want to put some beefy tantalum cap somewhere on 3V3 rail, something like 47uF or 22uF or at least 10uF - that would help to keep 3V3 steady in case when fast switches of levels are generated by MCU, for example and would smooth output ripple of regulator. I'm not sure how much current would your board draw but usually it's a good idea to have such cap on 3V3 or any other power rail along with bypass cap (100nF - 1uF).
I think I only have two electrolytic caps - 10uf and 100uf:
- https://www.digikey.lv/product-detail/en/panasonic-electronic-components/EEA-GA1C100B/P15786CT-ND/3831153 (https://www.digikey.lv/product-detail/en/panasonic-electronic-components/EEA-GA1C100B/P15786CT-ND/3831153)
- https://www.digikey.lv/product-detail/en/panasonic-electronic-components/EEA-GA1C101B/P15796CT-ND/3831163 (https://www.digikey.lv/product-detail/en/panasonic-electronic-components/EEA-GA1C101B/P15796CT-ND/3831163)
Will 100uf be good enough or I really need tantalum?
Final thought, I'm not sure if you have checked this document yet, but here's a full design documentation for SAMD51/E54 Xplained Pro board, I'd choose same decoupling caps on all the pins of the MCU to guarantee it's stable performance. I'm not saying your design is incorrect, but maybe you just want to check it against a real production board that uses such MCU. That's what I usually do in my designs. Hope this helps!
http://ww1.microchip.com/downloads/en/DeviceDoc/SAM_E54_Xplained_Pro_Design_Documentation.zip (http://ww1.microchip.com/downloads/en/DeviceDoc/SAM_E54_Xplained_Pro_Design_Documentation.zip)
All pins? I think I have decoupling cap on every power pin, did I miss something?
I have seen that and I have pdf open still... That board use 128 pin device, but I have 64 pin...
Just out of curiosity - why did you choose such a powerful and complex MCU? Do you really need it? Because there are models like SAMD21, SAML21 in a 32-pin package and with 48MHz and full-speed USB onboard, or even in a SOIC-14 package, if you don't need to many GPIO ports. Easier to do a PCB for these ones, easier to debug and with almost all features. FPU is great and 120MHz too, but as far as I understand - you just need to talk to RS485 bus and to display, I2C and SPI buses? All that can be achieved with SAMD2x/L2x MCUs without any trouble. Also, external crystals are only required if you really want a high-precision stability, from my experience I had no issues to use internal oscillators of these MCUs, didn't notice any significant (to my applications, including FreeRTOS) time drift, but they allow to save a lot of power if you're operating from a battery or switched into a battery backup mode. SAML-series MCUs are the best for lowest power applications. In regards to external crystals - you also want traces to them to be as short as possible and of equal length for best stability.
32 MHz xmega was not fast enough. Text was scrolling too "slow", I was hoping that I could workaround that by moving content by multiple positions at one time, but that had side-effect - text suddenly looks very bold...
I don't want to redo pcb if internal oscillator will not be good enough. That pcb will be outside of building and has to work in winter and/or summer and from what I have read temperature can affect stability.
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Sorry, of course not on ALL pins, on all power pins :) It's just often you can see a ferrite bead and a cap on VDDIO or other pins, sometimes - 2.2uF + 100nF caps for decoupling and some energy storage on VDDIO pin or VDD pin and so on. Even if you're using a 64-pin version it still worth a look at power supply lines, in a datasheet to your MCU it's pages 47-51, they recommend to use an inductor if you'd like to use switching power regulator for VDDCORE - it's much more efficient in switching mode, as I tested in my designs.
In regards to caps - you don't need electrolytic ones, tantalum or ceramic ones are just fine. You can put two 10uF ones next to each other to have 20uF and that's usually enough to keep power rail smooth and provide enough of 'fast' current in case when MCU needs it as voltage regulator might not be fast enough to react on a sudden change of current draw.
In regards to slow display scrolling - yes, I've had that before, but usually that's because of non-optimized display library and usually SPI still will not work on a speeds above 20MHz so no point in having a serial display and 120MHz MCU, have a look into datasheet for the top speed of I2C/SPI buses. If you're using a parallel display driver - that's when it all starts to work really fast. Also, you can use older SAM4L MCUs if you want high CPU frequency, FPU and other things but combined with low-power features.
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Also have a look at pages 2100-2102, see, there's a ferrite bead and multiple decoupling caps in the reference design. They have a 4.7uF + 100nF ones on VDDCORE pin, that's to ensure MCU has enough 'fast' current available if needed and to decouple, of course. Usually, though, I see a 2.2uF in XPlained Pro boards instead of 4.7uF ones for some reason. And there are two 10uF caps and 1uF one on VDDANA and VDDIOA/VDDIOB pins.
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Sorry, of course not on ALL pins, on all power pins :) It's just often you can see a ferrite bead and a cap on VDDIO or other pins, sometimes - 2.2uF + 100nF caps for decoupling and some energy storage on VDDIO pin or VDD pin and so on. Even if you're using a 64-pin version it still worth a look at power supply lines, in a datasheet to your MCU it's pages 47-51, they recommend to use an inductor if you'd like to use switching power regulator for VDDCORE - it's much more efficient in switching mode, as I tested in my designs.
I am not planing to use "Switching mode".
In xplained board 10uf capacitors is placed only on one vddana pin and one vddio pin, all other pins have only 100nf capacitors... So how can I decide on which pin to add extra capacitor? Randomly?
Anyway, I don't have 2.2uf and/or 4.7uf capacitors and I would prefer if I would not have to buy new things unless that is absolutely required. I found that I do have 10uf ceramic capacitors (1206 size). I don't have much free place without starting modifying layout. I could place one 10uf capacitor near C6...
In regards to caps - you don't need electrolytic ones, tantalum or ceramic ones are just fine. You can put two 10uF ones next to each other to have 20uF and that's usually enough to keep power rail smooth and provide enough of 'fast' current in case when MCU needs it as voltage regulator might not be fast enough to react on a sudden change of current draw.
I already have those. So can I place one 100uf electrolytic instead of two 10uf ceramic capacitors?
In regards to slow display scrolling - yes, I've had that before, but usually that's because of non-optimized display library and usually SPI still will not work on a speeds above 20MHz so no point in having a serial display and 120MHz MCU, have a look into datasheet for the top speed of I2C/SPI buses. If you're using a parallel display driver - that's when it all starts to work really fast. Also, you can use older SAM4L MCUs if you want high CPU frequency, FPU and other things but combined with low-power features.
I don't use existing libraries... :) So, yes, most likely it can be optimized, but I doubt doing that I would make it at least 2x faster.
SPI is not problem here, it correctly send data to display. Scroll speed is limited to how fast mcu can update content in back buffer and then move it to front buffer. With xmega I was using DMA to show content on display from front buffer.
Parallel display driver? I think you might be thinking about different displays... Display in this case is built from many P10 led modules (32x16).
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If you're not using switching mode - then Figure 56-2 applies to your design. Your package is 64-pin one, it has 3 VDDIO pins, each of them should have 100nF bypass cap plus VDDCORE should have a 2.2-10uF (you can use 10uF, shouldn't be an issue, instead of 4.7uF shown) cap + 100nF bypass one, plus VDDIO should have some 'energy storage' cap, shown as 1uF in Fig 56-2, ferrite bead is usually required with its caps. Have a look at table 56-1 - it describes everything in details. Yes, you can omit most of these caps, just use 100nF ones for decoupling and one bigger on 3V3 rail. As for me - 100uF is of a too high value, it will take time to charge it and may cause issues as it will be draining a lot of current to get charged. Here's what ferrite bead is for:
A ferrite bead has better filtering performance compared to standard inductor at high frequencies. A
ferrite bead can be added between the main power supply (VDD) and VDDANA to prevent digital
noise from entering the analog power domain. The bead should provide enough impedance (e.g.,
50Ω at 20 MHz and 220Ω at 100 MHz) to separate the digital and analog power domains. Make
sure to select a ferrite bead designed for filtering applications with a low DC resistance to avoid a
large voltage drop across the ferrite bead.
In regards to display driver - yes, I thought you're using a graphic matrix one, something like 320x240, there's a lot of popular display now, using both SPI and I2C and they're quite slow in serial mode. But you can easily get such display with a parallel connection mode utilising 16-bit mode and they're much faster. But this doesn't apply to your case, of course.
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What you are doing in the software may be of vital importance. I don't know the layout of the panels you have. I'd guess serpentine. That is first row one direction, then second row goes the opposite direction. It makes manufacture easier. That unfortunately messes up just using a double length buffer, and moving the start point in the buffer.
Next idea: Drawing buffer is like a ring buffer, but both in X and Y directions. To scroll, you change the start X/Y pointer, and only draw the part between the old and new location of the start point. A routine will need to be written to copy from the start point to the output buffer. It will need to wrap around to the beginning of the physical buffer when it reaches the end of the physical buffer. I'd also look into double buffering the output buffer. That way one can be displayed from using DMA while the other is being copied to.
A few notes:
* The drawing buffer can be larger than the display.
* Having the drawing buffer larger than the display may make it so the area being redrawn can be outside the currently actively displayed area.
* With the drawing buffer as an X/Y array, it should be possible to scroll up and down and left and right.
* If you want to have both fixed and scrolling areas, they can be implemented with separate drawing buffers. The copy to output buffer routine then selects which one to grab pixels from based on where it is writing into the output buffer.
* I've heard of this technique being done decades ago when computers were much slower. XWindows has routines to handle this. I know it existed before XWindows did.
In regards to slow display scrolling - yes, I've had that before, but usually that's because of non-optimized display library and usually SPI still will not work on a speeds above 20MHz so no point in having a serial display and 120MHz MCU, have a look into datasheet for the top speed of I2C/SPI buses. If you're using a parallel display driver - that's when it all starts to work really fast. Also, you can use older SAM4L MCUs if you want high CPU frequency, FPU and other things but combined with low-power features.
I'll second all of this. My setup is much different, and has much fewer LEDs. I'm not familiar with the drive requirements for your display panels, but I'm assuming an array of the panels you mentioned. My MCU dev board is a Teensy 3.6 which has a MK66FX1M0VMD18 Cortex-M4F ARM MCU at 180 MHz. On a 288 APA102 LED array I get free running almost 1000 calculate, and display cycles when using a simple integer math and very simple display calculations. Half my display is written at 8 MHz and the other half is at 4 MHz by the FastLED library. They are on two different SPI busses. I normally use floats to do all my arithmetic for HSV selection, and conversion to RGB, and my displayed images are much more complex than the simple integer test. It slows the update rate down to around 400 updates per second when free running. Normally I use a 120Hz update cycle. Most off my newer drawing objects are defined by mathematical functions, so I do a lot of floating point work. For them I just calculate the function values for HSV at the point on the display. No mixing of adjacent pixels for those objects, except at their edges. I need to work on the display speed, and make sure DMA is being used.
For hooking multiple APA102 strings to one SPI port I use TI 74HCT125 quad buffer chips. At 5 VDC they accept 3.3 VDC logic levels. Check the specs on them. I do think it is the HCT line.
For larger displays I'm thinking of dedicating 2 CPU cores to calculating the display on a multi core ARM chip like used in the Raspberry Pi. I'll have another core that handles the updating of the display, and gives the marching orders to the calculation cores. The last core will be left for running raspbian, reading the GPS, syncing time with time servers on the net, etc. Raspberry Pis have a nice fast SPI port that can drive up to 32MHz. I just wish I could get a 4 core one in a Pi Zero form factor. The normal format is to large for some of my artwork.
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What you are doing in the software may be of vital importance. I don't know the layout of the panels you have. I'd guess serpentine. That is first row one direction, then second row goes the opposite direction. It makes manufacture easier. That unfortunately messes up just using a double length buffer, and moving the start point in the buffer.
Display is built from 72 P10 modules that are placed in two rows. Each row is connected to controller and modules in row are daisy chained. Total display size in diodes is 1152 x 32. Module is divided in 4 groups and only one group is displayed - 1/4 scan rate or whatever is proper name for it...
Next idea: Drawing buffer is like a ring buffer, but both in X and Y directions. To scroll, you change the start X/Y pointer, and only draw the part between the old and new location of the start point. A routine will need to be written to copy from the start point to the output buffer. It will need to wrap around to the beginning of the physical buffer when it reaches the end of the physical buffer. I'd also look into double buffering the output buffer. That way one can be displayed from using DMA while the other is being copied to.
Hmm, sounds like something I could try. :) Right now existing content is moved left and new content appended...
So you suggest to use 3 buffers? One that is used for drawing and two for output? That can be problematic, xmega has 16 kb sram and one buffer needs 4.5 kb...
A few notes:
* The drawing buffer can be larger than the display.
* Having the drawing buffer larger than the display may make it so the area being redrawn can be outside the currently actively displayed area.
I was thinking about having buffer that could contain all content, but then sram is my problem.
* With the drawing buffer as an X/Y array, it should be possible to scroll up and down and left and right.
* If you want to have both fixed and scrolling areas, they can be implemented with separate drawing buffers. The copy to output buffer routine then selects which one to grab pixels from based on where it is writing into the output buffer.
Text just moves from right to left. Different areas are not needed. :) I am creating this controller because of two reasons/problems with controllers that was used with display:
- existing controllers could not scroll text fast enough.
- multiple things require separate areas. you can place temperature in one area, text in other, but client wants that all content scrolls as one big text. so one area with temperature, text, time...
Anyway I think that I will try to finish new pcb. I have updated it to add 4.7uF capacitor (c19) for VDDCORE. Added also 10uF (c20) capacitor and ferrite bead (l1) for VDDANA, and 47uF (C21) for 3V3.
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Anyway I think that I will try to finish new pcb. I have updated it to add 4.7uF capacitor (c19) for VDDCORE. Added also 10uF (c20) capacitor and ferrite bead (l1) for VDDANA, and 47uF (C21) for 3V3.
Sounds and looks good to me, should be much more stable now even in an environment with high noise!