TTL NAND gate from discrete transistors

[nand2025]

Thanks for all the replies - very interesting!

I spent a little more time making an AND gate and improving the layout on the breadboard.

Attached is a photo of the breadboard, along with the input and output waveforms at 1 MHz.

1 MHz was my original goal, so I'm happy with that.

Thanks for all the help in getting to this point!

 

[brucehoult]

That looks like about 40ns propagation delay, which is not bad.

Typical 5-stage pipelined (or 5 clock multi-cycle) RISC CPUs have around 30 gate delays per clock, so you might not be able to reach an actual 1 MHz operating speed with gates like that. On the other hand a borderline insane design such as the Pentium 4 was apparently around a dozen gate delays per pipeline stage -- that's just barely enough for a good 32 bit carry-lookahead adder.

[gcewing]

in the actual 7400, on which this diagram was based, Q1 and Q3 are one transistor with two emitters.

Interestingly, the LS TTL family seems to do without an input transisor at all and just uses a diode AND gate made from shottky diodes.

[chilternview]

Interestingly, the LS TTL family seems to do without an input transisor at all and just uses a diode AND gate made from shottky diodes.

Yes LS used diodes (schottky) as they were faster than multiemitter transistors and had higher breakdown voltages (the transistor reverse B/E breakdown voltage was only just better that the maximum supply voltage). The 74F series, which I worked on, had very thin base junctions, breakdown was typically 6v.