PCM1795 Reset Function

[avogadro]

Hello,

Im a bit confused with the power-on/external reset function of this DAC. In my circuit im using CS8416 as the receiver and I have the RMCK of CS8416 driving the SCK of PCM1795. Now the datasheet of the DAC says that the initialization sequence for resetting the DAC requires 1024 system clocks and after that the DAC is in its default reset state.

From my understanding this pin is only needed to set the registers in the device to their default states after power-on and these default states can be programmed before.

Now the problem is that CS8416 is outputting a clock on its RMCK pin only when its receiving audio data and this clock is sync with other data lines to the DAC (I2S). This means that there will be no SCK input to the DAC until the receiver starts receiving some audio data but ideally I should provide a separate clock to DAC just for setting the device to its default state.

So my idea is to have an MCU provide this clock and resetting the device then quitting after 1024 clock cycles. I would then have a high-speed buffer to select which clock is applied to the SCK pin (MCU or RMCK) but due to the delay in this buffer I would have to have all the data lines going through this buffer because they are in sync with this clock. Something like this is done in the TI development board but that board provides PC control and I think thats the main reason they have a solution like this. Also Im not sure if this delay will somehow affect the DAC.

Other idea is to have a MCU set all the registers over SPI on each power up and just forget about the RST pin but Im not sure if its necessary to run this reset function after power-up or after changing the registers.

I assume Im either overcomplicating this and theres a simple solution or Im just not understanding the datasheet that well.

Can somebody give me a better idea or correct me if Im wrong?

Also Im quite a big noob, this is my first proper project.