I can't recall in which article I read this, but it basically said that if a SOA graph for a FET only has a straight line between R_DS(On) and V_(BR)DSS area for DC, then the SOA graph should not be trusted for DC operation.
Attached is the SOA for the
IPP65R095C7, which has the characteristic kink in the graph the article talked about (and also at a more representative Tc).
Now, I'm no expert and I haven't had a chance to test this in practice yet unfortunately so can't say if the above FET is capable of linear loads. But compared to many other SOA graphs, it at least
looks much better than many others.