Crystal oscillator circuit for Sony image sensor

[bmxsesh]

Hello,

I am trying to build a circuit for Sony CXD3611R which seems to be a must have in order to be able to drive one of their CCD image sensors (ICX415AQ)
The datasheet seems to have a lot of missing information as for me, but regardless I am trying to understand what this circuit means
First, what could be a possible CKI capacitor value? 0.1 pF is my wild guess
Second, why would it divide the frequency by two? I picked a crystal SJK 7U29500E20UCG and the datasheet attached
Supposedly it takes a crystal oscillation for its PLL and should produce a 29.5MHz square clock on the MCKO pin for the image processor? But then why "1/2" which I assume is divide by two?

-bmxsesh

[lunar]

First, what could be a possible CKI capacitor value? 0.1 pF is my wild guess

Convert the crystal in the circuit into an equivalent resistance/inductance/capacitance electrical model and you can estimate what the impact a given capacitance will have on the circuit. It might help to have a VNA of some sort (maybe a nanoVNA will work). See:

[jwet]

Hello,

1> First, what could be a possible CKI capacitor value? 0.1 pF is my wild guess
2> Second, why would it divide the frequency by two? I picked a crystal SJK 7U29500E20UCG and the datasheet attached
3>Supposedly it takes a crystal oscillation for its PLL and should produce a 29.5MHz square clock on the MCKO pin for the image processor? But then why "1/2" which I assume is divide by two?

-bmxsesh

1 Coupling CKI is a coupling cap to couple the oscillator signal out to further stages.  I think they loop this out in case you want to add some circuits like dividers, etc or apply an external clock.  The cap should be a reasonable value to couple 29.5 MHz to the following amp at CKI.  I would think you'd want a reactance that could drive a little- 100 pF would be 53 ohms probably too much, perhaps 22 pF would be comfortable.  The amplitude at the CKI is specified as about .5v sine in the DS.

2/3 I don't think its dividing by two and that's not what these blocks mean.  I think it CAN divide by two but those 1/2 blocks are not just dividers, they are a divider with a data selector that let's either the input flow through or a divided by two signal flow through.  I noted that the clock path can go up to 50M, so when using a 50M xtal, you can divide by two.  I didn't see explicitly in the register table where this is set.  See if Sony has an applications guide for this stuff.  These docs are pretty thin.  Often the really good docs are in japanese but you can glean a lot "reading" them.