OK, so would you accept this as an accurate illustration of that distinction?
(Attachment Link)
It depends on whether the resistor is above or below the load, correct?
No. Your circuit is still supplying current to a load. Whether the current is positive or negative is irrelevant. It's a "source".
OK, so can someone please show me what a sink would look like? Preferably in schematic form? (Crayon on cocktail napkin sketch perfectly acceptable.)
A quick sketch, cut-and-pasted from a description of the 7404 TTL hex inverter. Note that this original form of TTL logic is an example of "current-sinking" logic, along with DTL. Later "TTL" types, including 74LS, are usually DTL.
Ignore the redundant labels from the original figure, but concentrate on the horizontal connection from the output of the left circuit to the input of the right circuit. This circuit normally operates in one of two states: "
Vhi" and "
Vlo" for the voltage on that wire, with corresponding currents along the wire in opposite directions. The two states are labeled with brackets for [hi] and {lo}. I added designators for Q1, Q2, and Q3. The two inverters could be on the same substrate or in two different packages.
I apologize for the bad image quality, but my crayon was dull.

Now, in the {lo} state (logic 0 at that node), Q2 is off and transistor Q1's collector is sinking current from transistor Q3's emitter. Q3 is powered from the Vcc node on the right. Since Q1 is saturated, it presents a low impedance to that current flow
Ilo sourced by Q3, and the voltage
Vlo is quite low.
However, in the [hi] state (logic 1 at that node), Q1 is off, and Q2 is a source pulling up the node to a higher voltage
Vhi. The current
Ihi for this IC series is much lower than
Ilo. Q2 is probably better considered a voltage source, rather than a current source, driving a relatively high impedance. Q2 is powered from the Vcc node on the left.
On the data sheet, the manufacturer guarantees certain voltage and current levels for the gate in isolation.
The suffixes below were changed to correspond to data sheet specs.
For the first gate's output supplying the second gate's input:
Voh > +2.4 V for
Ioh < 0.4 mA
Vol < +0.4 V for
Iol < 16 mA
The requirements at the second gate's input for definite logic levels are
Vih > +2.0 V at 0.04 mA and
Vil < +0.8 V at 1.6 mA
so there is some noise immunity at the high and low logic states.
From the low-state sink current of the first gate, and the low-state source current of the second gate, we quickly calculate that one output can certainly drive 10 inputs (10:1 fanout).
Incidentally, I have never seen the term "voltage sink", although "voltage source" is quite common. If one needed that term, it might be a relatively high-impedance load fed from the source.
A CMOS gate output is usually a switched voltage source driving a capacitive load at the driven inputs.