Electronics > Beginners
CurrentSense Comparators for electronic load
Vovk_Z:
You are right, here is full schematics with input voltage control:
T3sl4co1l:
I don't get it, why possible advantage does that system hold, that simply wiring transconductance stages in parallel (see above) does not provide?
I also don't understand the diagram, in that, I suspect you're showing things at a much higher level than they actually are..!? First off, comparators have no place in a linear circuit -- they are by definition the most nonlinear component. Changing gain implies at the very least an analog multiplier, which is terrifically over the top for a simple application like this, and again nonsensical in combination with a digital signal (a comparator output). It might not even be analog, it might be digital instead, in which case it's, I guess, some absolutely complicated mess of a distributed digital architecture, reading mismatch to update gain registers at some rate (every update strobe, perhaps) and... ohh man it's the beginnings of a horror movie! Or perhaps you've made the error of using the word "comparison" to mean "subtraction", and it's actually a difference amplifier, with well defined gain and bandwidth; but if this is the case, then why not label it as such? I have so little information to go on, I have to make far too many assumptions in order to begin to make sense of this!
Tim
Jwillis:
--- Quote from: T3sl4co1l on February 01, 2020, 01:59:19 pm ---I don't get it, why possible advantage does that system hold, that simply wiring transconductance stages in parallel (see above) does not provide?
I also don't understand the diagram, in that, I suspect you're showing things at a much higher level than they actually are..!? First off, comparators have no place in a linear circuit -- they are by definition the most nonlinear component. Changing gain implies at the very least an analog multiplier, which is terrifically over the top for a simple application like this, and again nonsensical in combination with a digital signal (a comparator output). It might not even be analog, it might be digital instead, in which case it's, I guess, some absolutely complicated mess of a distributed digital architecture, reading mismatch to update gain registers at some rate (every update strobe, perhaps) and... ohh man it's the beginnings of a horror movie! Or perhaps you've made the error of using the word "comparison" to mean "subtraction", and it's actually a difference amplifier, with well defined gain and bandwidth; but if this is the case, then why not label it as such? I have so little information to go on, I have to make far too many assumptions in order to begin to make sense of this!
Tim
--- End quote ---
I don't expect anyone to interpret the inner workings of the circuit based solely on a simple block diagram thrown together in a few minutes . The question was whether referencing the blocks in series would work any better over a parallel configuration. That's it. It was concluded that in a series configuration would probably compound errors.
I didn't include a circuit diagram because its a work in progress and experimental .
Because no matter how well you pick your components perfect balancing would not be possible since a tiny difference in threshold voltage between MOSFETs results in a substantial current mismatch . Other factors also effect the balancing like temperature and how well matched the other components are.
The use of differential comparators is is to increase or decrease the gain of each block based on an active current sense. Yes the output of the comparator is digital (either high or low). But I found that I can control the gain of each driver. By doing this the Mosfets balance much closer together than the conventional way without the need to perfectly match the components I have.
I have a working circuit on my bench doing exactly that. The reason I'm trying to keep the Mosfets balanced as accurately as possible is because of a limited amount resources to create an electronic load to handle very large current loads without any one mosfet falling out of the Forward Safe Operating Area (FSOA). Yes I could use more mosfets or different Mosfets .I could use more heat sinks But I don't have any of that available . So I'm working with what i have.
I have no doubt that that other circuits are adequate for what they are purposed for. And I'm sure that 5% variation is fine for many applications . But I wanted to see if I can try something that might work a little better . And so far it has . All my mosfets are holding within a couple degrees of each other with the currents holding within very small margins of each other. Which is better than how it was originally set up without active current sense and comparators . Better than I originally expected .
It's an experiment . If it works go with it . And I simply don't understand why trying to make something work a little better causes such a controversy.
T3sl4co1l:
See, that's my point, you're communicating something with the diagram, but what? It's a language thing -- can you rephrase it, or describe it some other way, or give something more concrete like a preferred implementation (granted that it's "in progress" and all)? That's all.
As for the description of the problem, "a pairwise balancing mechanism", yes, that is clear -- for a chained architecture, it will accumulate errors.
More generally, say you have N independent current sources, independent in that they're doing their own thing while operating at the same given setpoint. There are N^2 - N possible (directed) connections between them. Presumably there would be a way to connect them such that the error between any given pair is no greater than the error of a single correction circuit, and we would probably want to find connections which minimize the number of correction circuits for a given error.
So, if we draw the graph, plotting a node for each current source, and an edge between any two that are correcting in this way (and note that it's a directed graph when our correction circuit only works one way, from a reference to a destination), we can see that the chain architecture has the greatest maximum distance between any two nodes on the graph -- it's actually the worst possible!
If we rearrange instead for a star topology, we can use one node as the reference for the other N-1 nodes, and incur only one correction error at most. We still need N-1 correctors, and there isn't any obvious way to do better without leaving any nodes completely untouched. This falls short of a rigorous proof, but I'm comfortable with it.
Here's the trick though: say we declare that reference node is an abstract signal, not actually a current source; we add another current source to maintain the same total current, so now we have N correctors for N current sources with 1 reference. We can suck each corrector inside its respective current source, say integrating it into the driver circuitry. There may be some savings in component count / cost this way.
This now describes just any regular old opamp-per-FET architecture, wired up as needed to maintain accuracy. Mind, there might be two wires for setpoint and setpoint ref, to avoid ground loop errors where connections between shunt resistors can introduce errors. We might end up needing two or three opamps per stage to resolve the differential voltages (ref, shunt and gate drive), but that's fine.
We can use the same components in each unit, achieving arbitrary accuracy -- 1% is trivial and probably doesn't even need differential sense, 0.1% you need costly resistors and probably differential sense, 0.01% or better and you'll probably need to calibrate each section individually, perhaps even temperature correction as well.
So -- if this follows the scheme you were considering -- this should show that we can consider a superset of possible architectures, and more or less proves that the canonical architecture is already best.
Lastly; balancing... simply isn't an interesting problem. If you require better than 10% matching, your thermal management is woefully, and dangerously, inadequate! This should only ever be a design consideration, never an operating requirement!
You can add one more op-amp, outside of all the stages in parallel, to maintain total current equal to ref. This amp can be arbitrarily precise, while the imbalance between stages can be gross (but managed) -- this could greatly simplify the circuit, say by using relatively large source balancing resistors and no per-FET driver at all, as long as the higher minimum (saturation) voltage drop is acceptable. (Perfect for a high voltage CCS; for low voltages, you'd still want amp-per-FET.)
And you can always add thermistors to adjust local gate voltage, say; this would be a good idea if independent heatsinks are used. Wire it up so the thermistor dominates over the FET's natural tempco. Thermistors should be provided anyway to measure heatsink temp, and throttle down or disable operation if any one gets into a dangerous range.
Or, if the outputs aren't wired together, but they're for independent loads -- again, simply make each stage for the desired accuracy and that's that. :)
HTH,
Tim
Vovk_Z:
--- Quote from: Jwillis on February 02, 2020, 04:06:27 am --- And I simply don't understand why trying to make something work a little better causes such a controversy.
--- End quote ---
Because you tell us strange things - that comparators will be better then opamps (or precision opamps) in linear mode.
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