Cyclone V flashing LEDs and clock (Verilog)

[pmamatsis]

Hello everyone,
   i wanted to ask a 'dummy' type of question. I am trying (using Verilog) to flash the LED on my board (Terasic Cyclone V GX Starter Kit) and i am using a counter in my design (as suggested in my previous post by some people) in order to perform the clock down. From my understanding up to now (by reading the pdf board manual with the technical specifications) this board has a 50MHz clock which you can clock up or down using a PLL. Since i don't know how to use the PLL in order to clock down i have used a counter...if i wanted to use the PLL but i didn't wanted to use a Quartus MegaFunction is there any other way to synthesize the PLL? Do you believe that it is up to my level these kinds of questions?

I am sorry if my question sounds dummy but please go easy one me. I found out this world of FPGAs and AVRs etc. on an older age. 

Best regards and
thank you so much in advance.

[AndyC_772]

MegaFunctions are the way in which the dedicated hardware blocks in the FPGA are called up and configured. You'll need to use one to incorporate a PLL.

The wizard generates all the files you need in order to incorporate the dedicated hardware just like any other component. (Sorry, I can't help you with this... I speak VHDL and not Verilog).

[pmamatsis]

MegaFunctions are the way in which the dedicated hardware blocks in the FPGA are called up and configured. You'll need to use one to incorporate a PLL.

The wizard generates all the files you need in order to incorporate the dedicated hardware just like any other component. (Sorry, I can't help you with this... I speak VHDL and not Verilog).

Hi @AndyC_772,
   first of all let me thank you for your quick response. Oh!!! I see!!! This means that after adding a MegaFunction to my design for use the PLL i will be able to see the Verilog code that Quartus software will be using in order to synthesize the PLL, right? I only hope to understand even 1% of it!!!

Since i am now starting out with this (of course is a bit late to ask this question because i have already bought books about it...) why do more people using VHDL instead of Verilog? I have read the various resources on the internet for comparing both design languages but for a n00b's eyes like me i would expect more people to use Verilog because it's more "C-like"...

Best regards.

[AndyC_772]

You can read the code generated by the Wizard if you like, but you don't really need to. The code mostly contains the values for the parameters you've entered via the GUI, and if you're hoping for a complete equivalent circuit of the PLL written in Verilog, I'm afraid you'll be disappointed.

I'm not sure 'most' people use either one language or the other. I've heard it said that Verilog is more popular in the US, while VHDL is more popular in Europe, but I've no concrete evidence to back that up.

[John_ITIC]

Th Megawizard will generate the needed HDL to interface with the PLL hardware. You'll include this in your project and can also tell the Megawizard to generate an instantiation .v file, which you'll paste into your design. Essentially, this will have the 50 MHz clock input, the PLL output as well as a 'locked' output that tells you that the PLL has locked. In general, if you want to flash an LED then using a down-counter would be the correct approach though.

[pmamatsis]

Th Megawizard will generate the needed HDL to interface with the PLL hardware. You'll include this in your project and can also tell the Megawizard to generate an instantiation .v file, which you'll paste into your design. Essentially, this will have the 50 MHz clock input, the PLL output as well as a 'locked' output that tells you that the PLL has locked. In general, if you want to flash an LED then using a down-counter would be the correct approach though.

Good morning John_ITIC,
   thank you for your reply too. Of course i don't believe that i am going to understand even 1% of the generated HDL code behind the PLL in my current level of knowledge but i am just curious as to see what kind of HDL gets generated for a PLL MegaFunction.

Thank you all for your answers...my journey continues!!!

Best regards.