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D flip flop freq. devider

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miso156:
Thank you, one another question, in books i can see a Dflop made by NAND gates, but if I imagine to build freq. devider from this I always end up in oscilating during positive clk. Pls correct me If I am wrong.

When I start with Qneg 1, it put a 0 from upper NAND to Set pin of Dflop and switch Qneg to 0. Then the inverter put 1 to lower NAND with CLK still 1 it switch to Qneg to 1 again.

Pls correct me If I am wrong.


rstofer:
Let's suppose Q' = 1, Q = 0, D = 1 and Clk = 1
The top left NAND has both inputs = 1 so the output is 0.
The top right NAND has a 0 on one input so the output is 1 and Q just changed from 0 to 1 because D was 1
The lower left NAND gate has a 0 on the pin from the inverter (because D = 1) so the output is 1
The lower right NAND gate as ones on both inputs so the output is 0 which makes Q' = 0  and holds Q = 1

Now let's suppose Q' = 0, Q = 1, D = 0 and Clk = 1
The top left NAND has a 0 on the D input so the output is 1
The lower left NAND has 1's in both inputs so the output is 0
The lower right NAND has a 0 on the bottom input so the output is 1 and Q' = 1
The top right NAND has 1s on both inputs so the output is 0 and Q=0.  In addition, the output wraps around to the lower right NAND and holds it a '1'.

I don't see any reason for it to oscillate.

The logic values written on the drawing are wrong, the output of the inverter should be 0 because D = 1.  This error messes up the lower right NAND as well.

It's easy enough to set up an initial state, pick  a value for D and then let the clock be '1'.  Just walk it through.  I did 2 cases, there are two more:  D = 1 and Q is already 1 and D = 0 and Q is already 0.  Walk them through like I did above.

TerminalJack505:

--- Quote from: miso156 on February 04, 2020, 11:01:27 pm ---Thank you, one another question, in books i can see a Dflop made by NAND gates, but if I imagine to build freq. devider from this I always end up in oscilating during positive clk. Pls correct me If I am wrong.

When I start with Qneg 1, it put a 0 from upper NAND to Set pin of Dflop and switch Qneg to 0. Then the inverter put 1 to lower NAND with CLK still 1 it switch to Qneg to 1 again.

Pls correct me If I am wrong.




--- End quote ---

You are correct.  That is a Gated D Latch and it will allow the D signal to shoot through to the outputs when the enable signal (Clk) is high.

You can put two of these in series to create a master/slave configuration to build a D Type Flip-Flop.  The Clk signal is inverted (and slightly delayed) for the master.  This will cause only one of the latches to be enabled (= transparent) at one time.

Edit: Had Q and Qn swapped on the Gated D Latch schematic.

miso156:
Finally i did it. The master-slave work pretty good.



And the waveforms, where for two clock cycle it makes one period on the output.

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