Let's suppose Q' = 1, Q = 0, D = 1 and Clk = 1
The top left NAND has both inputs = 1 so the output is 0.
The top right NAND has a 0 on one input so the output is 1 and Q just changed from 0 to 1 because D was 1
The lower left NAND gate has a 0 on the pin from the inverter (because D = 1) so the output is 1
The lower right NAND gate as ones on both inputs so the output is 0 which makes Q' = 0 and holds Q = 1
Now let's suppose Q' = 0, Q = 1, D = 0 and Clk = 1
The top left NAND has a 0 on the D input so the output is 1
The lower left NAND has 1's in both inputs so the output is 0
The lower right NAND has a 0 on the bottom input so the output is 1 and Q' = 1
The top right NAND has 1s on both inputs so the output is 0 and Q=0. In addition, the output wraps around to the lower right NAND and holds it a '1'.
I don't see any reason for it to oscillate.
The logic values written on the drawing are wrong, the output of the inverter should be 0 because D = 1. This error messes up the lower right NAND as well.
It's easy enough to set up an initial state, pick a value for D and then let the clock be '1'. Just walk it through. I did 2 cases, there are two more: D = 1 and Q is already 1 and D = 0 and Q is already 0. Walk them through like I did above.