Electronics > Beginners

D flip flop freq. devider

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miso156:
Id like to design freq. devider by 2 using something like D flop build from PBJT.



But i dont like to use egde firering D flops, so it must hold the output by some another logic or something. Is there some solution?

Until now , I did something like figure below, but it of course oscilate due to immediate changes on D pin:

rstofer:
If you don't use edge triggering, what you have is a transparent latch.  Since you have negative feedback, as long as the latch input is enabled, the output continues to change state, it oscillates.

There's a reason that flops are edge triggered.

miso156:
Can you navigate me how level triggering can be achieved? Means that the change can occur only once per positive Clk.

Kleinstein:
A counter is always kind of edge triggered in one way or the other. One can just shorten the pulse so far that one only gets a very short pulse of something like 1 gate delay and this way get a kind of edge trigger with a circuit that otherwise looks like not explicitly looking for a edge.

With discrete transistors it is more the other way around and capacitove coupling could be used for the edge to get away with less transistors.

miso156:
THx, from some pherspective, it can be done by circuit  "turn on-off by one button". See:



However, i am looking for some solution without helping with condensators, only logic.

Until now get to solution like pic. below, when I use two Dflops. It should work like when 1st one is set, wait until CLK low to set a 2nd one, and in next positive cycle reset the 1st. Of course, its is not complete done yet.

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