DC amplifier circuit is oscillating

[Laval]

Hello everyone.

I'm prototyping an amplifier circuit using an op amp and an output MOSFET stage. The goal of that circuit is to amplify DC values. The reason for the MOSFET output stage is that it will eventually need to output up to 1kV otherwise the op amp alone would be fine.

For now I'm prototyping with only 20v supply to get a feel of the circuit behaviour. I'm using MOSFETs because it is possible to get some capable of driving 2kV+ which avoids having to piggyback a bunch of BJTs.

The problem I have right now is that it oscillates. As is, without capacitors, it oscillates steadily at about 58 kHz (I have a 100nF capacitor across the Vcc and GND pins of the op amp). Putting various capacitors values across R4 changes the frequency and amplitude but it still oscillates.

There must be some delay in the feedback loop, the MOSFET's gate is a capacitive load, but I'm not sure how to solve the problem.

[TimFox]

Have you tried capacitors across R5?

[Andy Chee]

Hello everyone.

I'm prototyping an amplifier circuit using an op amp and an output MOSFET stage. The goal of that circuit is to amplify DC values.

What is the required bandwidth of your amplifier?  You say 58kHz is bad, so insert a compensation network to roll off the gain above X kHz.

[Laval]

Have you tried capacitors across R5?

I did. In fact, that's the first place I tried because it is generally where you put them but it made things even worst. Admittedly, the smallest capacitor I have atm is 0.22nF which is a bit large. Maybe I need smaller caps like 10pF.

[Laval]

What is the required bandwidth of your amplifier?  You say 58kHz is bad, so insert a compensation network to roll off the gain above X kHz.
[/quote]

The amplifier will be used only for DC values.

[iMo]

You are creating 180deg phase shift in your circuit..
This may work better, imho..

[Laval]

You are creating 180deg phase shift in your circuit..
This may work better, imho..

Yes, thanks for the circuit. It is difficult to find BJTs that will operate at the 1 kV power rail it will eventually have to handle. I'm reading about compensation network like Andy Chee said, it's the problem.

[magic]

Configuring Q1 as voltage follower will not give 1kV.

As for the original circuit, the first thing is that stability will depend on Q1 stage gain and overall closed loop gain, i.e. the ratios R1/R2 and R5/R4. So set them to something realistic (100~200x or so, I guess) if you want your prototype to be realistic. Well, this may screw up DC bias of the prototype, so if it can't work, at least try to make the ratio (R1/R2)/(R5/R4) be realistic - I think near unity would be OK. This ratio goes into loop gain, so lower is more stable. But you need to mind things like Q1 gate voltage and available output swing of U1.

Then I don't know, perhaps try 10kΩ between the control voltage source and U1, plus a fairly substantial (dunno, 100nF or more?) local feedback capacitor around U1 (OUT to IN-). This is where playing with SPICE AC analysis could make sense. The big unknown is Q1 - it will have flat gain and close to 180° phase up to some frequency, then start to fall off and lag 270°. You want your overall loop gain to fall below unity by the time it happens, and the direct feedback around U1 should provide for that. I think.

An alternative option for high voltage is the old "boosted opamp" circuit which takes signals from the opamp's supply pins. Maybe slightly more complex than the above, provided that the above would work.

[tggzzz]

MOSFET SPICE models are notoriously deficient in some respects; some better ones contain an additional 14(!) SPICE primitive components. More hints in https://www.eevblog.com/forum/projects/lcsc-looking-for-spice-modals-436149/msg5596667/#msg5596667

Even if you have a good design that works well in SPICE, when constructed you might find that your circuit doesn't "care" that it is a DC circuit, but decides to be very "frisky" at RF

kV MOSFET circuits are described extensively in TAoE3 and especially TAoE3 X-chapters. You will save yourself a lot of time and grief if you obtain those references.

[Laval]

kV MOSFET circuits are described extensively in TAoE3 and especially TAoE3 X-chapters. You will save yourself a lot of time and grief if you obtain those references.

Yes indeed, there is an example of piezo driver at p209 (my third edition) which looks like my circuit but with a totem pole to get 0V output and a some sort of current limiter on the output follower. It also has an input buffer likely to increase the input impedance. There is not that many explanations but it is mentioned that a more detailed analysis is provided in the X chapter. I think it might be a good time to buy the X chapter, this is where the good stuff is.

Thanks to you and Andy Chee, lots of good advice and relevant information.

[magic]

SPICE would help quickly get some idea about global loop stability, and maybe not much more.
For that, the important part is that Q1 and Q2 capacitances are in the right ballpark.

[Laval]

SPICE would help quickly get some idea about global loop stability, and maybe not much more.
For that, the important part is that Q1 and Q2 capacitances are in the right ballpark.

In AoE, they are using a feedback loop on the inverting op amp (between the output and the inverting input). This loop has a capacitor on the feedback resistor and one between the feedback resistor and the output. This is, I think, local feedback to roll off the gain of the op amp when frequency is above the some value. I tried it and for a moment it stopped oscillating. The accuracy went up (even better my target accuracy) but it started to oscillate again.

I wasn't able to find some Spice model for the MOSFET I'm using but I'll try again and order some capacitors in the tens of pF. Thanks.

[Zero999]

You are creating 180deg phase shift in your circuit..
This may work better, imho..

Yes, thanks for the circuit. It is difficult to find BJTs that will operate at the 1 kV power rail it will eventually have to handle. I'm reading about compensation network like Andy Chee said, it's the problem.

The IRF540 doesn't work well at 1kV either.

kV MOSFET circuits are described extensively in TAoE3 and especially TAoE3 X-chapters. You will save yourself a lot of time and grief if you obtain those references.

Yes indeed, there is an example of piezo driver at p209 (my third edition) which looks like my circuit but with a totem pole to get 0V output and a some sort of current limiter on the output follower. It also has an input buffer likely to increase the input impedance. There is not that many explanations but it is mentioned that a more detailed analysis is provided in the X chapter. I think it might be a good time to buy the X chapter, this is where the good stuff is.

Thanks to you and Andy Chee, lots of good advice and relevant information.

You'll get more helpful replies, if you kept it to one thread, rather than starting a new one.

Your DC amplifier has a large gain. It would help if you reduce it by applying negative feedback, before the op-amp. Use the circuit I posted in the other thread, but with MOSFETs, rather than BJTs.



It will still need a frequency compensation network, but will be much easier to stabilise.

Transistors can also be cascoded to increase the voltage rating, but it's much easier to just use a single high voltage part.

[basinstreetdesign]

The problem I have right now is that it oscillates. As is, without capacitors, it oscillates steadily at about 58 kHz (I have a 100nF capacitor across the Vcc and GND pins of the op amp). Putting various capacitors values across R4 changes the frequency and amplitude but it still oscillates.

There must be some delay in the feedback loop, the MOSFET's gate is a capacitive load, but I'm not sure how to solve the problem.

There is indeed some delay in the feedback loop.  The op-amp isn't getting enough feedback at higher (>100 KHz) frequencies.  Your circuit should work just fine with a small adjustment: put a nominal-valued resistor inseries with the inverting input (say start with 5K but could be anywhere from 1K to 25K) and a small-valued cap (say 100 pf to 1nf) between the output of the op-amp and its inverting input.  That will make sure the op-amp has lots of feedback at 1 MHz and up and prevent it from slewing too far while its waiting for feedback from R4/R5.

[magic]

Your DC amplifier has a large gain. It would help if you reduce it by applying negative feedback, before the op-amp. Use the circuit I posted in the other thread, but with MOSFETs, rather than BJTs.



It will still need a frequency compensation network, but will be much easier to stabilise.

This too may work and be easier maybe, if the Q2/Q1 local loop doesn't go nuts. You test this loop in isolation by simply rewiring U1 to unity gain.

If it works, you then stabilize the whole lot with the usual trick: capacitor from OUT to IN- and resistor from IN- to the feedback divider.

[CaptDon]

The circuit proposed by the O.P. would have a hard time scaling up to 100v and will never see 1KV!! I do like some of the BJT circuits other posters have submitted.

[Laval]

I have tried the circuit posted by @Zero999 using MOSFETs instead of BJTs. It's a very interesting circuit. It is also oscillating but it doesn't seem to bother the resulting output much. At a higher input voltage, the magnitude of the oscillation went up but the accuracy didn't suffer a lot. I added a compensation network as proposed by @basinstreetdesign and tuned the cap. I settled for a 10k resistor and two 0.22nF caps in series (to get about 0.11nF). It considerably decreased the magnitude of the oscillation, smaller caps might improve the situation a bit. I'll order some with a few OPA189 (that op amp has an impressive spec and is quite cheap). With the compensation, accuracy improved slightly.

The accuracy of the circuit is about 0.14% which is one order of magnitude lower then my target (ideally 0.01%). The interesting thing is that the accuracy is very constant across the whole range of input values unlike my circuit. This would make a calibration possible. This is an impressive circuit especially considering its simplicity.

I am picking up a lot of noise. I had to use my dual channel linear lab power supply (which is very quiet) to power the op amp and I had to use a small bench SMPS to power the transistor stage. That power supply is very noisy. I have put a few decoupling caps on the transistor stage power rail as well as on the op amp power rails. It decreased the noise a bit but not that much. Maybe I should use some ferrite bead on the rails.

The circuit proposed by the O.P. would have a hard time scaling up to 100v and will never see 1KV!!

That's correct and consistent with what I observed but I had to try. I don't have the experience you guys have with this.

[Laval]

Since that small SMPS is very noisy I tried powering up the transistor stage with batteries and it was actually good in term of noise and oscillation. I guess a proper PCB would likely help a lot in this regard, it would definitely be better then a parasitic ridden breadboard.

I need to improve the accuracy. I suspect the op amp is unable to adjust sufficiently small "increments" or maybe the compensation isn't good enough yet. I hand-picked the two resistors of the outer feedback loop, they are very close to the specified values (less then 1% error on resistors). But the inner loop isn't.

[TimFox]

Linear IC op amps do  not have “incremental” behavior, but do have finite (albeit huge) DC gain

[Laval]

Linear IC op amps do  not have “incremental” behavior, but do have finite (albeit huge) DC gain

Of course. That was a bad choice of words on my part. I didn't mean incremental in the sense of steps, I know feedback is a continuous process.

[iMo]

Interesting circuit, indeed..
Without the C1 (its value randomly chosen) it oscillates a little bit at around 120kHz.

PS: the input signal is a sine 1Vpp at 2.5V offset, and the gain is set 200.
Output is the sine at 500V offset with 200Vpp.

[Terry Bites]

Q1's gate capacitance is not isolated from the opamp. I'd add a small resistor say 100R. Slip a ferrite bead over the gate lead.

[Laval]

Q1's gate capacitance is not isolated from the opamp. I'd add a small resistor say 100R. Slip a ferrite bead over the gate lead.

Which of the designs ? With the first one where Q1 is common source, yes. I'm reading an application note from AD about that. But how do you size the ferrite bead ?

[dietert1]

I think iMos last proposal V2 is close if you add the 100R resistor into the G1 gate connection.
The circuit will still oscillate as it has two mosfets with high impedance drive in a loop. At high frequencies capacitors dominate and there may be 2x 90° shift which means oscillation.
If you make the output divider 995K / 5K into a frequency compensated divider, adding two capacitors, it should become stable. Like 100 pF and 20 nF for a gain of 200. The capacitive divider adds fast drive to the lower mosfet input capacitance. The lower cap of the divider can be smaller or omitted as the input capacitance of the mosfet can be 500 pF up to several nF, see the mosfet datasheet.

Regards, Dieter

[PGPG]

My 3 cents...
Typical OpAmp has a dominating pole at very low frequency (like 10Hz) and gain set to such value that it reaches 1 at about the frequency that other poles began to shift phase.
So when gain is 1 it alone (OpAmp) gives 90° shift (by dominating pole) and may be 45° shift by other poles near frequency at which gain crosses 1. This allows to set gain of 1 connecting output to (-) input having phase margin may be 45°.
Now at first schematic the gain is increased 10x so even added elements introduces no poles the amplifier will be no stable with gain = 1. If gain would be set to 10 than the loop would have the same ch-c as OpAmp alone and could be stable (I all the time assume extra x10 gain introduces no new poles what is not true). But with whole gain set to 3 it has loop gain of 3.333 at the frequency where OpAmp designers assumed it have to be max 1.
As some extra circuits are needed and additional gain is also needed than extra poles are inevitable.
I think the solution should be to shift dominating pole down (for example from 10Hz down to 0.1Hz). I think it can be done by introducing circuit having pole at 0.1Hz and zero at 10Hz (to compensate original OpAmp pole).
The other solution can be to decrease OpAmp gain (with local feedback) to reach by the whole circuit the gain of 1 at lower frequency (before all new poles introduced by external circuitry).