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| DC dummy load circuit calibration |
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| Ian.M:
Rs for each MOSFET is shown as {1/5} i.e. five x one ohm resistors in parallel. The complexity is the price you pay for demanding accuracy at low currents without being willing to pay for high performance OPAMPs, or 0.1% E192 series precision resistors. Shorting each MOSFET g-s to disable three of them is simple if you include four 0.1" pitch two pin headers to put jumpers on. N.B. with them shorted their OPAMPs will drive a small current (limited by the 1K gate resistors) through your low-side current shunt, so you should measure the 1mA with an external meter in series with the load. The interaction between the overall range trim and individual offset trims is slight. If you roughly set up the range trim with all the offset trims set to 0V at their wiper then trim the offsets, then go back and fine-tune the range it will be plenty good enough. I assume anyone serious has E12 1/4W 5% or better resistors between 1R and 1Meg in stock. If not, you'll have to improvise with series/parallel combos. The six caps (two decoupling + one per OPAMP in the feedback loop) are unavoidable if you want to avoid it oscillating. 100pF is just a best guess for the feedback cap - you'd need to build one MOSFET + OPAMP loop and check what value gives the best step response. In the sim, 820pF looks good, with a critically damped minimal overshoot step response. If you are feeding Vctrl from a 10K pot, you'll need to buffer it with an OPAMP like Dave's design did if you want good linearity. Unfortunately that takes us back to needing very good OPAMPs or a 7V or higher Vcc supply to them if you want a full 0-5V for 0-5A control range. Averaging the voltages across the four sense resistors to get the total current would need some calibration, and possibly compensation for the offset voltage of the buffer OPAMP. However if you were adding a MCU, that could easily be handled in software. In fact if you were using a MCU to generate the control voltage, you could discard the individual offset trim pots and replace them with a single one just to set 0mA at 0mV as linearisation at low control settings could be handled in software. However, as you are using a panel meter, you don't have to worry about all that - your only concern is the panel meter accuracy. If you decide to experiment further with the 2N2222 gate pulldown current limiting idea, to avoid the last digit jumping around as the limiting cuts in and out, you need to locate your panel meter so the gate pulldown current does *NOT* flow through it. e.g. put it between the circuit 0V rail and the negative terminal for connecting the external supply you are testing. A further note - rather than attempting to linearise and calibrate either circuit for very low currents, it is probably preferable to use a fifth MOSFET, OPAMP 10R sense resistor and 5:1 input divider, which gives you a basic sensitivity of 20mA per V, then use a DPDT range switch to apply the control voltage to either the high range four MOSFET circuit or the low range single MOSFET circuit, and switch the unused circuit's input to the negative rail to guarantee its cut-off and not drawing any current. The extra MOSFET can share a heatsink with any of the other ones, and the extra components will certainly be cheaper than the multi-pole precision high current switch that would be required to switch in different sense resistors for the main set of MOSFETS. |
| VEGETA:
You mentioned accuracy at lower current such as <10mA, so I am asking... does it mean we cannot get these currents at all or just some error? like you want 10mA and get 11mA or so? I need to remind you, since I am using a panel meter that means such very good accuracy is not needed. All I need to do is to calibrate the panel meter itself. As long as I can get 1 mA output and read it on the panel meter (supports only 10mA range, so it is 10mA minimum accuracy for the whole project) then I am OK. I told you that I want 1V per 1A which is still valid, but I would not worry too much about accuracy in the < 10mA range since I am using a panel meter. So a rough 1V\1A is nice enough for this project. --- Quote ---I assume anyone serious has E12 1/4W 5% or better resistors between 1R and 1Meg in stock. If not, you'll have to improvise with series/parallel combos. --- End quote --- I think I will make combos, like 1k||1K = 500. I think this 500 seems to have a relationship with 1v\1a right? I tried to make it 1k and it didn't work. --- Quote --- The six caps (two decoupling + one per OPAMP in the feedback loop) are unavoidable if you want to avoid it oscillating. 100pF is just a best guess for the feedback cap - you'd need to build one MOSFET + OPAMP loop and check what value gives the best step response. In the sim, 820pF looks good, with a critically damped minimal overshoot step response. --- End quote --- How about 1nF for opamp caps and 1uF for decoupling? I guess all ceramic caps will be good enough. I don't have oscilloscope (nor the knowledge) to test such circuits. 1nF seems nice value and a common one, if not, then 10nF or so. --- Quote ---If you are feeding Vctrl from a 10K pot, you'll need to buffer it with an OPAMP like Dave's design did if you want good linearity. Unfortunately that takes us back to needing very good OPAMPs or a 7V or higher Vcc supply to them if you want a full 0-5V for 0-5A control range. --- End quote --- So only 10-turn pot and that is it. However, 5A is gonna be massive. Like, putting 30v x 5A = 150 W -> 37.5 Watts per branch! No way the heatsink will be able to dissipate that. I think 30v\2A is very nice... 15 watts per branch -> = 0.2*2*2 = 0.8 watts in Rs which is good. If I didn't get a big heatsink (my friend promised one) then it is back to 1.5A. I could just use a voltage divider before the 10-turn pot to make the range. simulation shows 4.3V on Vcc and it will be true since I will use 1N4001\7 diode (-0.7v drop)... then 1k + 1k divider gives 2.15 maximum voltage which means around 64.5 watts maximum in worst case. --- Quote ---However if you were adding a MCU --- End quote --- Not in this version, probably in future upgrade like Scullcom design. You still didn't comment about it BTW. :-// --- Quote ---If you decide to experiment further with the 2N2222 gate pulldown current limiting idea, to avoid the last digit jumping around as the limiting cuts in and out, you need to locate your panel meter so the gate pulldown current does *NOT* flow through it. e.g. put it between the circuit 0V rail and the negative terminal for connecting the external supply you are testing. --- End quote --- I still don't understand why its current will interfere in the circuit. Is there anything else wrong with this method besides this? All I understand is the gate will have a voltage, then if current is increased this voltage will increase which activates the transistor to pull the gate of mosfet down. However, my values are different than original design (he used 47k) but I think the voltage will be Vbe/0.2 but how did you calculate it? I mean, if current makes voltage very slightly more across 0.2R then how does this equal to the amount we need to keep it regulated between all 4 branches? how to determine that? |
| VEGETA:
I've been trying to make a negative rail (using npn with resistors) to make circuit go down to 0A but I couldn't with the 5v rail supply. The positive supply will not be enough to let the op-amp drive the mosfet gate to give 1.5A. Thus, I will keep it at ground potential... Actually even by this, there is some inaccuracy at lower currents but I won't be measuring anything so it won't matter. I am gonna build up the circuit in KiCAD now... If you have any final notes please write them |
| Ian.M:
I suggest you draw up and lay out the circuit as-if your OPAMP is good enough to get enough output swing to support having a negative rail, but build it without the resistor that provides the bias current to the NPN Vbe multiplier, without the Vbe multiplier resistors , without the negative rail decoupling cap and with a wirelink E-C in place of the NPN. That lets you build it for now with a single supply for the OPAMP, but if you manage to obtain a better OPAMP, or decide to power it from a higher voltage wallwart, you can remove the wirelink and fit the parts you left out, to improve the circuit's performance at low currents. Please feel free to post GIFs or PNGs of your PCB layout + final schematic for comment - its much quicker, easier and cheaper to get us to bug-check your design rather than finding out the hard way that the PCB you have ordered has design or layout problems. As its only the two of us currently participating in this topic, you may wish to start a new one for the PCB design to get more opinions. |
| VEGETA:
--- Quote from: Ian.M on May 16, 2018, 11:01:53 pm ---I suggest you draw up and lay out the circuit as-if your OPAMP is good enough to get enough output swing to support having a negative rail, but build it without the resistor that provides the bias current to the NPN Vbe multiplier, without the Vbe multiplier resistors , without the negative rail decoupling cap and with a wirelink E-C in place of the NPN. That lets you build it for now with a single supply for the OPAMP, but if you manage to obtain a better OPAMP, or decide to power it from a higher voltage wallwart, you can remove the wirelink and fit the parts you left out, to improve the circuit's performance at low currents. Please feel free to post GIFs or PNGs of your PCB layout + final schematic for comment - its much quicker, easier and cheaper to get us to bug-check your design rather than finding out the hard way that the PCB you have ordered has design or layout problems. As its only the two of us currently participating in this topic, you may wish to start a new one for the PCB design to get more opinions. --- End quote --- It is ok for me to build a final circuit now, then if I want to do a modification I will make an entirely new one. So I will build it as it is. I guess no negative rail for now since it won't work with this op-amp and this circuit as I tested in LTSpice. Your latest simulation worked but since we don't want any complicated calibration stuff, then I don't think I will use it. I will make the PCB schematic and post it here as .png and the whole kicad project too. |
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