DC on mosfet SOA graph?

[Ionforbes]

Hello all,

I have some IRL2910 mosfets which I want to use as a DC load. Each MOSFET will have to sink a max of 5A. I looked at the attatched SOA graph in the datasheet and it seems the longest period specified is 10ms, unless I'm interpreting it wrong? I put some labels on it to show what I think the graph is saying. I plan to disspiate no more than 20W per TO-220 FET, knowing this I could try to to work out the max voltage with thermal resistance calculations. However this wouldn't take hot-spotting into account whereas the SOA graph would I think.

So my questions are: am I reading the graph wrong, and does the graph take hot spotting into account?

Many thanks,
Ion

[TimFox]

In the first table of the datasheet for that device we see two important lines:
  P_D = 150 W at T_C = 25 C (case temperature)
  Derate factor  1 W/K:  for DC reduce the above rating by 1 W per degree above 25 C.
The SOA graphs show what can be tolerated for short times, but the above two are for DC.
On log-log scales (as in the SOA graph you posted), that derated 150 W limit would be another straight line, but the choice of line depends on the heat-sinking, since the case temperature rises with power by a substantial amount that is under the control of the designer, not the manufacturer.

[Ionforbes]

Thanks for the reply. The unit will consist of a heatsink with 0.4K/W, with 5 FETs attatched that dissipate 20W each. Junction-case is 1K/W and case-heatsink is 0.5K/W. Ambient here never exceeds 30, so 0.4*100 + 30 =70 degrees on the heatsink. Then each transistor loses 20W so 70 + 20*0.5 + 20*1 = 100 degree junction temp. Using the 2 lines you pointed out, 150-100 = 50W max, so they're definitely safe for absoloute temperature then.

However, how would I account for hot-spotting? Do I even need to worry about it so long as power dissipation is wthin spec?

[TimFox]

The manufacturer’s specs for static operation should govern DC operation, using your calculations.  Is 30 C max ambient literally true?  Today’s forecast for outdoor temperature in Chicago is 35 C.
There is a thread here from 2012 about hotspotting in linear mode that seemed to minimize the problem with MOSFETs, which are not subject to second breakdown at high voltage, as seen in BJTs.  Past that, you should check the semiconductor literature.

[Ionforbes]

It's a personal project and will be indoors and houses here never reach 30 C even in summer and there's fan so the air is always fresh and cool.

However, I looked at some app notes and I looked for the point where the temperature coeff. for drain current vs gate voltage becomes negative, and it happens at a gate voltage of 3.2V. My FETs will be sinking only 5A each, so gate voltage will probably be a bit below that and the FETs will in fact be thermally unstable 

I've looked for FETs where the temperature crossover point happens below the required gate voltage, but haven't found any. In fact I looked at one of Dave's teardowns of a BK precision load, and their IRFP250N FETs have the crossover at a gate voltage of 6.4V at which point the saturation current is 35A, so setting the load to current below that would cause hot spotting, right?

Am I missing something? How did BK get away with it?

Thanks,
Ion

[TimFox]

In a feedback circuit, the temperature co-efficient of the gate voltage -- drain current should be compensated by the feedback, unless somehow you reach a limit on control voltage.
Be careful about your ambient temperature:  if the circuit and heatsink are contained inside a box, a fan is probably necessary for 30 C.
(I am old enough to remember otherwise-good audio amplifiers in the early days of solid-state high-fidelity that had bad thermal design.)

[Ionforbes]

Thanks for the reply,

Of course, I somehow forgot to consider the feedback loop  . Good to know I didn't waste my mone on all those FETs.

And yes, there will be a fan with lot of forced airflow on the heatsink.

[T3sl4co1l]

There's not a lot to be determined from gross outward characteristics, unfortunately.  It's a micro to mesoscopic (die-scale) effect, so depends on design (geometry and formulation of the transistor cells) as well as construction (their distribution, and the packaged die assembly).

If they don't give DC SOA, keep shopping.

You can test it and plot some points yourself, but expect to need more than a few spares to explore much area.  For example, a while ago I tested a SiRF740 up to almost double its minimum Pd rating (worth checking, as old IRF740 datasheets claimed DC SOA (I think?) but don't anymore); not sure why they give such a wide range for RthJC, but it seems the minimum value actually applies.  The die inside the failed part was pretty large, suggesting they never die-shrunk this old design; which explains the apparently conservative rating.

Amazingly, modern SJ MOSFETs (you can tell by the extremely steep drop in Coss vs. Vds at low voltage) typically have DC SOA ratings, despite world-record highest power density in class.  Even more amazingly, some IGBTs are even getting DC ratings, and they seem to be serious -- this despite IGBTs having even higher power density than MOSFETs, plus even more thermally-unstable physics inside.

And it's the power density that matters -- the instability effect is always there, it's just a matter of whether it goes into runaway or not.  There's always a threshold, power level and temperature, where it happens.  When that threshold is beyond the package ratings, it's considered "free from 2nd breakdown".  It's not really, but for any practical purpose, I mean, how are you gonna know?

So it's also common to see small devices (like TO-92s and SMTs) with DC SOA, without any obvious indication that the die is special.  They simply can't dissipate enough power to get into the danger zone.  Or fullpacks, which can carry quite large dies, but have poor dissipation ability due to the surrounding plastic case (TO-220s limited to about 30W).

Oh, and SJ and IGBT only apply at high voltages (>300V or so); lower voltages are handled by more conventional designs, and this is reflected by their differing Coss(Vds) and SOA curves.  But lower voltages also mean lower power densities, so it's not hard to find full SOAs there.

Tim

[Vovk_Z]

some IRL2910 mosfets which I want to use as a DC load.

There is a siple rule: almost all 4-digit marked MOSFETs (2910) are "more next" generation of MOSFETs, I mean they are seriously optimized for switching mode, and they are usually very bad choice for DC mode (it can be seen from SOA all of them).
The good choice for electronic DC load are most of three-digit marked MOSFETs - for example, IRF240/250/260/350/450/460 etc.
So, yours IRL2910 is not good for DC load in general but is fine for 20 W device.

[Vovk_Z]

So my questions are: am I reading the graph wrong, and does the graph take hot spotting into account?

As for SOA: from my experience, we may find approximate DC SOA from a graph where there isn't a DC region stated. I show you how to do it on your figure, look at the attachment. But if there isn't a DC curve on a SOA - it is a possible key that this exact MOSFET is not good for DC mode operation.

[Whales]

In the first table of the datasheet for that device we see two important lines:
  P_D = 150 W at T_C = 25 C (case temperature)
  Derate factor  1 W/K:  for DC reduce the above rating by 1 W per degree above 25 C.
The SOA graphs show what can be tolerated for short times, but the above two are for DC.
On log-log scales (as in the SOA graph you posted), that derated 150 W limit would be another straight line, but the choice of line depends on the heat-sinking, since the case temperature rises with power by a substantial amount that is under the control of the designer, not the manufacturer.

Doesn't this give you crazily high performance figures, ie much better than even the 10ms SOA rating?

[tszaboo]

Generally, if they don specify DC, it might not work properly in DC, heat up, hotspotting, thermal runaway.
If they specify DC, there are SOA, which is not always S (safe). They might be specifying it that your device, the die is at room temperature, which is impossible in real world. So even with a SOA, you have to ask (and test) yourself if it is actually safe.
There is a lesser known definition of this, not a lot of manufacturers use it: FBSOA, stands for Forwards Bias Safe Operating area. That means that it will not hotspot and thermal runaway.
Also from what I understand at the same power, low voltage and high currents these are lesser problems than the other way around.
It is possible to pick FETs that run reliably "forever" at a certain point, which is not defined in the datasheet. I did that myself. But, If you want to save yourself from a lot of testing, it is better to pick something that has that definition. IXYS, Microsemi has linear FETs that do this, start there.

[Ionforbes]

Based on everyone's advice, I searched a bit and found the FDP2532. It has a fully specified forward bias DC SOA, and my needs are well within its spec

Interestingly, its 'thermal crossover' happens at at Vgs of 5.5V, at which point the drain current is 130A, so in theory it'd be prone to hot spotting/thermal runaway I think, but the SOA says I'm fine so I won't complain. They're a bit pricey but nothing like those dedicated linear FETs.

[Berni]

Yep as people said if there is no DC line on the SOA graph then do not use it for linear operation.

In practice you sometimes can do it. If you derate it down well enough say a 100W dissipation rated mosfet running at only 10W on good cooling. It also helps if you do it at low voltage since the runaway tends to be more prone near the top of the voltage rating.

As for "I ran my MOSFET near the 10ms line and it worked fine", its completely possible you got a lucky piece of silicon that happened to be uniform enough to not start the runaway, good chance some will blow up if you try getting 20 new mosfets and putting them trough the same thing. Some non DC rated mosfets also happen to work pretty well in the linear region, but the manufacturer didn't bother to characterize them for it. You see those mosfets used in some of the cheaper electronic loads, in that case they probably characterized a sizable population of those MOSFETs in the lab to make sure they can handle it.

[TimFox]

In the first table of the datasheet for that device we see two important lines:
  P_D = 150 W at T_C = 25 C (case temperature)
  Derate factor  1 W/K:  for DC reduce the above rating by 1 W per degree above 25 C.
The SOA graphs show what can be tolerated for short times, but the above two are for DC.
On log-log scales (as in the SOA graph you posted), that derated 150 W limit would be another straight line, but the choice of line depends on the heat-sinking, since the case temperature rises with power by a substantial amount that is under the control of the designer, not the manufacturer.

Doesn't this give you crazily high performance figures, ie much better than even the 10ms SOA rating?

The crazily high performance would occur if you could keep the case at 25 C.  The derate factor will give you a curve well to the left of the 10 ms rating.